JPH04199440A - CPU simulator - Google Patents

Abstract

PURPOSE:To display the data stored in a variable length register by the designated register length by changing the display form of the data through a display form switch part based on the information received from a register length monitoring part. CONSTITUTION:A register length monitoring part 3 is provided to monitor the length of a variable length register 4. Then a display form switch part 6 to change the display form for the data stored in the register 4 based on the information given from the part 3 is provided. Thus the data stored in the register 4 are displayed by a length equal to the designated register length. In such a way, the display form can be changed for the data stored in the register 4 based on the information given from the part 3 and the data are displayed by the designated register length.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention simulates instructions for a CPU that has a variable-length register configuration and is provided with means for specifying the length of the variable-length register. The present invention relates to a CPU simulator that displays data in registers.

Prior Art FIG. 3 is a block diagram showing a conventional CFIU simulator. In FIG. 3, reference numeral 1 denotes a simulator section (not shown) for simulating instructions of an 0 CPU, and 2 is a register length designation flag connected to the simulator section 1 to designate the register length of a variable length register. 3 is a register length monitoring unit that is connected to this register length designation flag and monitors its status; 4 is a variable length register buffer that is connected to the simulator unit 1 and into which data in the variable length register is written; is the maximum register length within the variable length range. Reference numeral 5 denotes a register display section connected to this variable-length register buffer 4 and displaying its contents.

The operation of the second conventional CPU simulator is as follows. In FIG. 3, when the simulator unit 1 simulates a CPU instruction that specifies a register length, the state of a register length designation flag 2 is set. When the simulator unit 1 simulates an instruction to read/write the contents of a register, the contents of the variable-length register buffer 4 are specified according to information from the register length monitoring unit 3 that monitors the state of the register length specification flag 2. Read/write for the specified register length. The register display section 5 displays all the contents of the register buffer 4 corresponding to the maximum register length within the variable length range. In this manner, the conventional CPU simulator displays only the maximum register length within the variable length range, regardless of the specified register length.

Problems to be Solved by the Invention However, in the conventional CPU simulator described above, even if the register length of the variable-length register is specified as a value other than the maximum length,
There was a problem in that the contents of the register could only be displayed for the maximum register length.

The present invention solves such conventional problems, and aims to provide a CPU simulator that can display the contents of variable-length registers for a specified register length. .

Means for Solving the Problems In order to achieve the above object, the present invention includes a register length monitoring unit that monitors the register length of a variable-length register, and a register length monitoring unit that monitors the register length of a variable-length register based on information from the register length monitoring unit. A display format switching unit is provided to switch the display format of the internal data.
When displaying data in a variable-length register, only the specified register length can be displayed.

Therefore, according to the present invention, by switching the display format of data in a variable-length register based on information from the register length monitoring section, ``the data in the variable-length register is displayed by the specified register length.'' can be displayed.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of a CPU simulator according to the present invention. The same reference numerals are given to the same parts as in the conventional example shown in FIG. 3, and the explanation thereof will be omitted as appropriate. In FIG. 1, 1 to 5 are the same as the conventional example. Reference numeral 6 denotes a display format switching unit that switches the display format of data in the variable-length register buffer 4 based on information from the register length monitoring unit 3.

Next, the operation of the above embodiment will be explained. In the above embodiment, when the simulator unit 1 simulates an instruction to set the register length, the register length designation flag 2
The state of is set. Next, when the simulator unit 1 simulates an instruction to read/write the contents of a register, the variable-length register buffer is Read the contents of 4 for the specified register length/
Write. The display format switching unit 6 switches the contents of the variable-length register buffer 4 to the display format by the specified register length based on the information from the register length monitoring unit 3. Display in the switched display format. FIG. 2 is a diagram specifically showing the relationship between the register length designation flag and display contents in the above embodiment. In Figure 2, register length specification flag 2
When the value of is 1, the length of the variable length register is 8 bits, ○
In this case, the length of the variable length register is specified to be 16 bits. Furthermore, when 8-bit length is specified, it is assumed that only the lower 8 bits of the data in the variable-length register buffer 4 are used, and the upper 8 bits remain unchanged. If the value of the register length designation flag 2 is O as shown in ■ in Figure 2, the register length is 16 bits, and 16 bits of data in the variable-length register buffer 4 is displayed. When the value of length specification flag 2 is set to 1, the register length becomes 8 bits, and variable length register buffer 4
The upper 8 bits of the data within are not displayed, but only the lower 8 bits are displayed.

In this way, according to the above embodiment, the register length monitoring unit 3
Based on the information from the variable-length register buffer 4, the display format switching section 6 switches the display format of the data in the variable-length register buffer 4 and displays it on the register display section 5. Only the register length can be displayed.

Effects of the Invention As is clear from the above examples, the present invention has the following effects. In other words, by switching the display format of the data in the variable length register using the display format switching unit based on information from the register length monitoring unit, it is possible to display only the specified register length of the data in the variable length register. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a CPU simulator according to the present invention, FIG. 2 is a diagram showing the relationship between the register length designation flag and display contents in the embodiment of FIG. 1,
FIG. 3 is a block diagram showing a conventional CPU simulator. 1...Simulator section, 2...Register length specification flag, 3...Register length monitoring section, 4...Variable length register buffer, 5...Register display section, 6...Display format agent Name: Patent Attorney Akira Okaji Baka28 No. 1
Figure 2 ■ ■ 24

Claims (1)

[Claims] a simulator section that simulates CPU instructions, which has a variable-length register configuration and means for specifying the register length of the variable-length register; and a register connected to the simulator section that specifies the register length of the variable-length register. a register length specification flag, a register length monitoring unit connected to the register length specification flag to monitor its status, and a register length monitoring unit connected to the simulator unit to write data in the variable length register, and write the data within the variable length range. A variable-length register buffer having a maximum register length in a display format switching unit that switches the display format of data in the variable length register; and a display format switching unit connected to the display format switching unit that specifies the contents of the variable length register buffer in the display format switched by the display format switching unit. A CPU simulator equipped with a register display section that displays only the registered register length.