JPH04199634A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention manufactures a semiconductor device including a polycrystalline semiconductor region and an amorphous region formed when impurities are implanted into the polycrystalline semiconductor region. It is about the method.

[Prior Art] Currently, DOPO3 (Doped Poly-3), a polycrystalline silicon emitter whose emitter can be fabricated by a self-line process, is the most suitable bipolar transistor (BPTI) for achieving shallower junctions and higher integration.
i) BPT is known tail. (1) DOPO3BP
T is also used as a wiring element, and ion implantation is a method for injecting impurities into polycrystalline silicon to construct a semiconductor device.

[Problem to be solved by the invention] However, in the conventional ion implantation method of implanting impurities into polycrystalline silicon, the ion implantation conditions and post-implantation heat treatment temperature are not optimal, so the electrical resistance of the obtained polycrystalline silicon is large. It has the disadvantage of becoming. This effect is particularly noticeable in low-temperature processes aimed at making junctions shallower.

An object of the present invention is to provide a method for obtaining a semiconductor device that has low resistance and can realize shallow junctions.

[Means and effects for solving the problem] The method of the present invention provides a DOPO3BPT using a polycrystalline silicon emitter.
By increasing the acceleration voltage when ion-implanting impurities into polycrystalline silicon, the entire polycrystalline silicon becomes amorphous, and by optimizing the heat treatment temperature for subsequent crystal recovery, polycrystalline silicon can be improved. This makes it possible to reduce resistance. That is, when the entire polycrystalline silicon is made amorphous, solid-phase growth is performed from the substrate side during heat treatment, so that a region with a large crystal grain size and a high activation rate can be obtained.

In the method of the invention, the thickness of the polycrystalline silicon region;
The relationship between the thickness of the amorphous region formed when impurities are implanted into the polycrystalline silicon region is extremely important, and the above effect is achieved only when this relationship is within a predetermined range. According to experimental results, when impurities are ion-implanted so that the thickness t of the polycrystalline semiconductor region and the thickness Xc of the amorphous region satisfy the relationship 0°8t≦Xc, a semiconductor having desired characteristics can be obtained. It turned out that the device was obtained. Further, when ions are implanted under the above conditions, heat treatment can be performed at a low temperature of 600°C to 650°C.

[Example] Hereinafter, an example in which the method of the present invention is applied to manufacturing a bipolar transistor will be described with reference to FIGS. 1A to 1E. First, a SiOx film 102 having a thin gate oxide film at a predetermined portion is formed on the surface of a silicon substrate 101, and then ions are implanted through this gate oxide film to form a p+ base 103 (see FIG. 1). A
). Next, 10 SiO□ films are deposited to a thickness of 04000~ at a temperature of approximately 400°C using the usual CVD method (
Figure 2B). The thickness of this SiOx film 04 is determined by the impurity ions implanted into the polycrystalline silicon in the step 2.
In this example, the thickness is set to an extent that can prevent As) from penetrating through and changing the thickness of the base surface.

Next, the gate oxide film of the SiO* film 102 and the SiO2
A direct contact is formed on the film 104 by photoetching (FIG. 1C). On top of this direct contact, a polycrystalline silicon layer 105 is deposited to a thickness of 2000 nm at a temperature of approximately 600° C. using the low pressure CVD method, and then As is implanted at a dose of 5E15 to 500 nm using the ion implantation method. IE16/crrl', acceleration voltage 150K
eV ~ 200 Keν and 1 at a low temperature of about 650 °C.
Heat treatment is performed for a period of time (FIG. 1D). The amount of As implanted determines the conditions for making polycrystalline silicon amorphous.
In this case, it is 3E14/crrI' or higher. Then, by buttering the polycrystalline silicon layer, the DOPO
A 3BPT emitter 106 is formed (FIG. 1E).

FIG. 2 shows the relationship between the accelerating voltage for As ion implantation and the sheet resistance value of polycrystalline silicon. The injection amount is 5E1
5/err? As described above, the thickness of the polycrystalline silicon film was 2000, and the heat treatment conditions were 800° C. and 1 hour. As shown in Figure 2, at an accelerating voltage of 150 KeV to 200 KeV, a device with a sheet resistance value significantly lower than that under conventional low accelerating voltage conditions was obtained. This is done to a depth of approximately 2E19/ctrl'. In addition, the implantation conditions are As concentration approximately 5E15/
crt? In the case of an accelerating voltage of 150 KeV, the depth Xc of the amorphous layer is about 1600 layers, so when the thickness of the polycrystalline silicon is t, the sheet resistance sharply decreases when the condition of 0.8t≦XC is satisfied.

FIG. 3 shows the relationship between the heat treatment temperature after As ion implantation and the sheet resistance value of polycrystalline silicon. The injection amount is 5E15/
cni, acceleration voltage is 150 KeV, polycrystalline silicon film thickness is 2000 keV, and heat treatment conditions are 8°0° C. for 1 hour. As can be seen from FIG. 3, a low sheet resistance value was obtained at a low temperature of 650°C.

Further, FIG. 4 shows the relationship between the accelerating voltage and the depth Xe of the amorphous layer in the case of As (Ge) ion implantation.

In the above embodiment, an example was shown in which As ions were implanted as impurities into polycrystalline silicon, but the same effects as in the above embodiment can be obtained even in the case of other ion implantations. The critical implantation amount of various ions for forming an amorphous layer is as follows.

B10 + 2X10”/ crdp+:
lXl0”/crrrAs+: 3X
10”/crdSb+: lXl014/c
rr? [Effects of the Invention] As described above, according to the present invention, the thickness t of the polycrystalline semiconductor region and the thickness Xe of the amorphous region are 0.8t≦
By ion-implanting the impurity so that the relationship of

[Brief explanation of the drawing]

1A to 1E are explanatory diagrams showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a graph showing the relationship between the acceleration voltage of As ion implantation and the sheet resistance value of polycrystalline silicon. Figure 3 is a graph showing the relationship between the heat treatment temperature after As ion implantation and the sheet resistance value of polycrystalline silicon, and Figure 4 is a graph showing the relationship between the heat treatment temperature after As ion implantation and the sheet resistance value of polycrystalline silicon.
3 is a graph showing the relationship between acceleration voltage and amorphous layer depth XC in the case of s (Ge) ion implantation. 101 is a silicon substrate, 102 is a 5in2 film, 103 is a base, 104 is an Si, 02 film, 105 is a polycrystalline silicon layer, and 106 is an emitter. Agent: Patent Attorney - Shimo Jo Taira 1st Diagram 2: Tori Hayakun. Ishiyo (me (eVn figure 3 fever)

Claims (2)

[Claims] (1) In a method of manufacturing a semiconductor device including a polycrystalline semiconductor region and an amorphous region, the thickness t of the polycrystalline semiconductor region and the thickness xC of the amorphous region are 0.8.
A method for manufacturing a semiconductor device, characterized in that the impurity is ion-implanted so that t≦xC. (2) Into the ion-implanted polycrystalline semiconductor region,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the low temperature heat treatment is performed at a temperature of 0°C to 650°C.