JPH04200111A - Pulse stretcher circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse stretcher circuit, and more particularly to a pulse stretcher circuit for stretching arbitrary pulses.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional pulse stretcher circuit. In the figure, αυ is a pulse input terminal, 02 is a clock input terminal (13a).

(13b), (13c), and (+3n) are D flip-flop circuits, Q4) is an OR element that takes the logical sum of the outputs of each D flip-flop circuit, and 09 is an output terminal.

Next, the operation will be explained. A pulse for one clock period is input to the first D flip-flop (DFF) (13a). The "H" level of the pulse is taken in at the rising edge of the first clock, and the first DFF output (K) is
The level changes from "rL" to "H" level. At the rising edge of the second clock, the first DFF output level (K) is instantaneously at "H". The second DFF takes this in, and the output (L) changes from "L" to "H" level.

Similarly, at the rise of the third clock, the output level of the third DFF changes from "L" to "H".

In this way, the output level of the n-th DFF changes from "L" to "H" at the rising edge of the n-th clock.
+1 clock rises and changes from "rH" to "L". Here, when the first to nth DFF outputs are logically summed, a pulse having a length n times the clock period is generated from the rising edge of the first clock.

Figure 4 shows the waveform when three DFFs are used. By taking the logical sum of the first, second, and third DFF outputs, an output pulse with a time width three times the clock period can be obtained. is obtained.

[Problem to be solved by the invention]

Since the conventional stretcher circuit is configured as described above, unless the input pulse width is equal to the clock cycle, the expansion ratio for the input cannot be set to a freely multiple. Further, there is a problem that an output pulse cannot be output from the time of pulse input to the first rise of the clock.

This invention was made to solve the above-mentioned problems, and aims to provide a Knolls stretcher circuit that can output a pulse width with an arbitrary magnification for an arbitrary input pulse width. purpose.

[Means to solve the problem]

The pulse stretcher circuit according to the invention connects two input terminals to the input of a first AND element, connects the output of this first AND element to the input of a first counter, and connects the two input terminals to the input of a first AND element. The output of the first counter is connected to the input of the multiplier, the first input terminal and the output terminal are connected to the input of a second AND element, and the output of the second AND element is connected to the input of the second AND element. Connect the output of the multiplier and the second counter to the input of the comparator, and connect the output of the multiplier and second counter to the input of the comparator.
- The output part of the one-shot circuit is connected to the input part of the one-shot circuit, and the output part is connected to the reset input part of the first counter and the multiplier.

[Effect]

The pulse stretcher circuit in this invention generates an input sampling and inputs it to the converter as a numerical value representing the degree of pulse width stretching using a counter and a multiplier. Further, the sampling value counted by one of the counters is also input to the comparator, and an expansion pulse is output while the value for expansion is reached from the initial state.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a pulse input terminal, (2) is a sampling pulse input terminal, (3) is an AND element that outputs input sampling, (4) is a counter that counts the number of input samplings, and (5) is an input terminal. (6) is a multiplier that performs a multiplication operation on the sampling number; (6) is a second AND element that cuts the output until the sampling pulse starts to be output; (7)
) is a second counter that counts the number of sampling pulses output by the AND element (6), and (8) compares the numerical value output by the multiplier (5) and the numerical value output by the counter (7), and calculates the difference between the two. A comparator that outputs "L" level when the numerical values are equal and "H" level when they are not equal, (9) is when the comparator output changes from rHJ to "L",
A one-shot circuit α0) that outputs a reset signal to the counter (4) and the multiplier is an output terminal.

Next, the operation will be explained. Figure 2 shows A shown in Figure 1.
A timing chart ranging from point to point is shown.

A sampling pulse shown in waveform (B) is always input to the second input terminal (2). At this time, the first input terminal (
When a pulse (A) is input to 1), the first AND element (
3), the AND is performed and the input sampling (C) is obtained. Here, the width of the input pulse (A), that is, the time during which the input pulse is at the "H" level, has a relationship with the number of input samplings as shown in the following equation.

T++ #nXts --■ The number of input samplings is counted by the first counter (4). This counted value (D) is input to the multiplier. Here, the multiplier set in the multiplier (5) corresponds to the pulse width expansion ratio. The example in FIG. 2 is a timing chart in which this multiplier is set to 2. When the output (E) of the multiplier is input to the comparator (8), the output (H) of the comparator (8) becomes the [H] level. At this time, the second AND element (6) connected to the comparator output opens its gate to the sampling pulse. At the same time, the reset signal for the second counter (7) is also released. Therefore, from this point on, the number of sampling pulses begins to be counted by the second counter (7). When the output (E) of the multiplier and the output (G) of the second counter (7) become equal, the comparator output goes from "Hj" to "L" level. At this instant, the reset signal (1) passes through the one-shot circuit (9) to the first counter (4) and the multiplier (
5). Further, the second AND element (6) and the second counter (7) are also brought to an initial state by the comparator (8) output signal.

Here, if the multiplier set in the multiplier (5) is m, the comparator (8) determines whether the output of the second counter (7) or m
The rHJ level is output until n.

If the time from when the second counter (7) starts operating to when it reaches mn is defined as T2c, the following equation can be expressed.

T2C#mn

〔Effect of the invention〕

As described above, according to the second invention, it is possible to obtain a pulse width with an arbitrary magnification (integer multiple) for an arbitrary pulse.

[Brief explanation of the drawing]

Fig. 1 is a system block diagram showing a pulse stretcher circuit according to an embodiment of the present invention, Fig. 2 is a timing chart diagram of a stretcher circuit according to an embodiment of the invention, and Fig. 3 is a system block diagram showing a pulse stretcher circuit according to an embodiment of the present invention. A system block diagram showing a Letcher circuit, and FIG. 4 is a timing chart diagram of a conventional pulse stretcher circuit. In the figure, (1) is a pulse input terminal, (2) is a sampling pulse input terminal, (3) is an AND element, (4) is a counter, (5) is a multiplier, and (6) is a second AND element. ,(
7) is the second counter, (8) is the comparator, (9)
is a one-shot circuit, and 00) is an output terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A first AND element having two input terminals connected to an input part, a first counter having an output part of the first AND element connected to an input part, and a first counter having two input terminals connected to an input part; a multiplier having an output part connected to an input part; a second AND element having the first input terminal and the output terminal connected to the input part; and a second AND element having the output part of the second AND element connected to the input part. a comparator having the output part of the multiplier and the second counter connected to the input part; and a comparator having the output part of the comparator connected to the input part and the output part of the first counter and the multiplier connected to the input part. A pulse stretcher circuit with a one-shot circuit connected to the reset input.