JPH0420169U - - Google Patents

Info

Publication number
JPH0420169U
JPH0420169U JP5861190U JP5861190U JPH0420169U JP H0420169 U JPH0420169 U JP H0420169U JP 5861190 U JP5861190 U JP 5861190U JP 5861190 U JP5861190 U JP 5861190U JP H0420169 U JPH0420169 U JP H0420169U
Authority
JP
Japan
Prior art keywords
flip
flop
gate
register circuit
closes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5861190U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5861190U priority Critical patent/JPH0420169U/ja
Publication of JPH0420169U publication Critical patent/JPH0420169U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Microcomputers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案によるレジスタ回路の一実施
例を示す回路図、第2図は第1図の動作説明に供
する各部の波形を示すタイムチヤート、第3図は
CPU周辺の回路構成例を示すブロツク図、第4
図は従来のレジスタ回路の一例を示す回路図であ
る。 15,18……フリツプフロツプ、19……O
Rゲート。
Fig. 1 is a circuit diagram showing an embodiment of the register circuit according to this invention, Fig. 2 is a time chart showing waveforms of various parts to explain the operation of Fig. 1, and Fig. 3 shows an example of the circuit configuration around the CPU. Block diagram, 4th
The figure is a circuit diagram showing an example of a conventional register circuit. 15, 18...flipflop, 19...O
R gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データをラツチする第1のフリツプフロツプと
、この第1のフリツプフロツプを一度書きにする
ためクロツク入力パルスの制御をするORゲート
と、このORゲートの開閉を行う第2のフリツプ
フロツプとを備えてなることを特徴とするレジス
タ回路。
A first flip-flop that latches data, an OR gate that controls a clock input pulse to write data to the first flip-flop once, and a second flip-flop that opens and closes the OR gate. Characteristic register circuit.
JP5861190U 1990-06-01 1990-06-01 Pending JPH0420169U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5861190U JPH0420169U (en) 1990-06-01 1990-06-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5861190U JPH0420169U (en) 1990-06-01 1990-06-01

Publications (1)

Publication Number Publication Date
JPH0420169U true JPH0420169U (en) 1992-02-20

Family

ID=31584381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5861190U Pending JPH0420169U (en) 1990-06-01 1990-06-01

Country Status (1)

Country Link
JP (1) JPH0420169U (en)

Similar Documents

Publication Publication Date Title
JPS59177235U (en) Pulse width delay circuit
JPH0216617U (en)
JPS6028723U (en) metal mirror
JPH02108438U (en)
JPS5866434U (en) Operation board
JPS6087658U (en) L type wrench
JPS6344265U (en)
JPS6320623U (en)
JPS6091073U (en) pillow with alarm clock
JPH0369931U (en)
JPS59128909U (en) nail
JPS59175592U (en) makeup opening frame
JPH0480131U (en)
JPH0455646U (en)
JPS6338420U (en)
JPS6024598U (en) push pin
JPS6085440U (en) Digital temperature compensated piezoelectric oscillator
JPS59133213U (en) medicine box
JPS5865907U (en) Goby
JPS6013535U (en) Data imprint control device
JPS5871800U (en) Piezoelectric buzzer drive device
JPS5847194U (en) electronic clock
JPS5828441U (en) Constant generator circuit
JPS6115834U (en) flip-flop circuit
JPS59160277U (en) Finger satsuku