JPS5956741A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the process by forming isolation regions different in depths by the one time patterning and etching processes. CONSTITUTION:A n<+> type silicon layer 12, a n type silicon layer 13, an SiO2 film 14, an Si3N4 film 15 and a PSG film 16 are formed on a P type silicon substrate 11. Then a mask is formed on an element forming region 18 including a collector isolation region 17 and the films 16, 15, 14 on the region 19 are removed. Thereafter, the film 16 on the region 17 is removed. The entire part is etched by the reactive ion etching method. After removing the film 16, the groove of the regions 17, 19 is filled with the SiO2 film 20 and polycrystalline silicon film 21.

Description

Detailed Description of the Invention (n) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, in particular, a semiconductor integrated circuit (r(;)) in which a U-shaped groove is formed between an element isolation region and a collector isolation region at the same time. Regarding a new manufacturing method for forming.

0]) Conventional technology and problems Previously, silicon nitride (S.j-siJ+) rt3
f: Used] OP (ISOlatiOrlW
A method of forming an isolation region between elements is known, in which the isolation region is etched to form a U-shaped groove, and the inner surface is etched. silicon dioxide (Si.O.)
This is a method of forming a film and burying the inside of it with polycrystalline silicon.

However, recently, the collector isolation region has also been formed into a U-shaped groove, and the inside of the groove has been similarly filled with Si-Cl. A method of embedding a film and a polycrystalline silicon film is used. FIG. 1 shows a cross-sectional view of the process, in which 1 is a P-type silicon substrate, 2
is a 11 + type silicon crystal layer (this is the buried layer of the semiconductor element), 3iJ. For such a silicon substrate, the collector isolation region 4 is an n-type silicon crystal layer (this is the region where the base and emitter are formed) and has a depth that reaches directly above the n-type silicon layer 2 or in the middle of that layer. , and the inter-element isolation region 5 has a depth that reaches the P-type silicon substrate 1. The reason why the collector isolation region is formed by dielectric isolation in this way is that it is possible to form a wall base (W) (ed. Ba. Se) 6 as shown in the figure, which reduces the collector base junction area and reduces stray capacitance. This is because the collector isolation region does not necessarily have to be of the 10P type in which polycrystalline silicon is buried, but may be an isoplanar type in which only a SiO film is formed.

However, as mentioned above, since the collector isolation region 4 and the element isolation region 5 have different depths, grooves are formed separately, and therefore two patterning and two etching steps are required. That only makes the process more complicated.

(C) Object of the Invention The present invention proposes a manufacturing method that aims to shorten such forming steps.

('') Structure of the invention The purpose of the invention is to grow a semiconductor layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, and on its upper surface:
A process of depositing an insulating film that can be etched away using the same etching Nl as the sbl4 film and having a small etching ratio, and then depositing a protective film on top of it, and then the above protective film on the collector isolation region. and further selectively remove the protective film and the insulating film in the element isolation region, and then the entire surface is simultaneously etched by reactive ion etching to form different depths in both regions. This is accomplished by a manufacturing method that includes the steps of forming a U-shaped groove and then removing the entire surface of the protective film.

(e) Embodiment of the invention Hereinafter, one embodiment will be described in detail with reference to the drawings. 2 to 5 show cross-sectional views in the order of steps according to the present invention. First, as shown in FIG. 2, a P-type silicon substrate 11 is coated with a film thickness of 1. An 11" type silicon layer 12 with a thickness of 5 pm and an n type silicon hηl3 with a thickness of 1.5 μm are epitaxially grown, and an
S.O*IIψ14 and film thickness 0.35μ〃j. 'i. J
J41) An insulating film consisting of 5' is formed, and a protective film consisting of a PSC film 16 having a thickness of 17z??+ is deposited thereon by chemical vapor deposition (CVJ-). As shown, the S1-Os film 4 is a buffer layer interposed between the Sj-a film and the Sj-a film so as not to damage the silicon substrate surface.

Next, as shown in FIG.
8) PSG film 16, S. LN41
1! ;3 15 Oyohi SiOgv14fT-ffngl:jt is removed, and then another resist film mask (not shown) is formed again to expose the collector isolation region 17 and mask other regions. Then, only the PSG film 16 on the collector isolation region 17 is etched away by wet etching using hydrofluoric acid or reactive ion etching using CHFs gas.

Next, as shown in Figure 4, carbon tetrachloride (Ccl.)
When all 11M are simultaneously etched by accu-dip ion etching using a mixed gas of 1 Torr and 650 W of pressure reduction using a mixed gas of U-shaped i{. } can be made to reach the silicon layer 12, and at the same time, the U-shaped groove of the element isolation region 19 can be made to penetrate through the n+ type silicon layer and reach the P-type silicon substrate 11. That is, since the etching ratio of the mask material consisting of SisN+n+; Mi 15 and SIOs++"lK 14 and silicon is 1:4 to 5, the film F
? :0.15 to 0.3 5 = 0.51l'n of mask material is etched away on the collector isolation region 17, while the inter-element isolation region 19 TidO. 5/”X(
4-5) = 2-2.5 μm f7) When the silicon layer is etched, and the etching progresses further and the 1] type silicon layer with a film thickness of 1,5/Inl is etched away in the collector isolation region, the element isolation occurs. Similarly in area 19, 1.
5pm thick etched cut (2
~2.5//”)+1,5 //+#=8.5-4/
A tmOU type U% is formed.

Therefore, when the JJ-shaped groove in the collector isolation region reaches the 10-type silicon layer, the U-shaped groove in the element isolation region reaches the P-type silicon substrate 11. At this time J] SG i1
j4 1 6, SlaN6Ifnjl5 and Si
The element forming region 18 covered with the mask material made of -os film has a film thickness of . Because of the 5/''' mask, the silicon must be etched to a thickness of 6 to 7.5 microns to be exposed. Therefore, the element formation region is sufficiently masked. Simultaneous window opening in both regions is
Since both windows have small steps, the opening process is easy and can be formed with high precision.

Next, as shown in FIG.
16 by etching with hydrofluoric acid, the inter-element isolation region 17 and the collector isolation region 1 are removed by the well-known TOP method.
Si, film 20 and polycrystalline silicon ii;'
Bury it with +21. Moreover, instead of the cross-sectional structure shown in FIG. 5, only the SiOg film may be buried by the CVD method.

In the above embodiment, the insulating film is 8181
'14 film and the protective film is a PSG film, but other insulating films or protective films may be used. In this case, it is desirable that the insulating film and the protective film be etched with the same etching agent, thereby simplifying the etching process.

(f) Effects of the Invention As can be seen from the above explanation, according to the present invention, JU-shaped grooves with different textures are formed at the same time by etching, which shortens the manufacturing process and has a positive effect on improving yield and quality. It gives

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the process of forming an element isolation region and a collector isolation region. Are figures 2 to 5 related to the present invention? FIG. In the figure, 111 is a P-type silicon substrate, 2.12 is n-type silicon}; , 7, 3.13 is an RL-type silicon layer, 4.17 is a collector isolation region, . 5
, 19ir. f inter-element isolation region, 14Sj○ film, 5
denotes S:L3N<film, 16 denotes PS G type''S, and 18 denotes an element formation region.

Claims (1)

[Claims] growing a semiconductor layer of an opposite conductivity type on a semiconductor substrate of one conductivity type;
A step of depositing on the upper surface an insulating film that can be etched away with the same etching agent as the semiconductor layer and having a lower etching ratio than the semiconductor layer, and further depositing a protective film thereon;
Next, selectively removing the protective film on the collector isolation region, and further selectively removing the protective film and the insulating film on the element isolation region, and then etching the entire surface simultaneously by reactor ion etching, A method for manufacturing a semiconductor device, comprising the steps of forming U-shaped grooves with different depths in the collector isolation region and the element isolation region, and then removing the protective film from the front side.