JPH0420662U - - Google Patents

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Publication number
JPH0420662U
JPH0420662U JP6137090U JP6137090U JPH0420662U JP H0420662 U JPH0420662 U JP H0420662U JP 6137090 U JP6137090 U JP 6137090U JP 6137090 U JP6137090 U JP 6137090U JP H0420662 U JPH0420662 U JP H0420662U
Authority
JP
Japan
Prior art keywords
switch
buffer amplifier
crystal oscillator
switches
stopped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6137090U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6137090U priority Critical patent/JPH0420662U/ja
Publication of JPH0420662U publication Critical patent/JPH0420662U/ja
Pending legal-status Critical Current

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Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、この考案によるマスタークロツク切
換回路の一実施例を示す構成図である。 １，２，ｎ……発振回路、３……加算回路、１
１，ｎ１……バツフアアンプ、１２，ｎ２……イ
ンバータ、Ｘ１，Ｘｎ……クリスタル発振子、Ｓ
Ｗ１ａ，ＳＷ１ｂ，ＳＷｎａ，ＳＷｎｂ……スイ
ツチ。 FIG. 1 is a block diagram showing one embodiment of a master clock switching circuit according to this invention. 1, 2, n...Oscillation circuit, 3...Addition circuit, 1
1, n1...Buffer amplifier, 12, n2...Inverter, X1, Xn...Crystal oscillator, S
W1a, SW1b, SWna, SWnb...Switch.

Claims (1)

【実用新案登録請求の範囲】 クリスタル発振子と、バツフアアンプと、外部
からの制御信号により相補的な動作を行う第１と
第２のスイツチとを有する複数個の発振回路を備
え、 前記制御信号の供給による前記第１のスイツチ
の動作に基づいて前記バツフアアンプからのクロ
ツク信号を前記第１のスイツチを介して出力する
とともに、 前記第２のスイツチの動作に基づいて前記バツ
フアアンプの動作を停止させて発振回路動作を停
止せしめることを特徴とするクロツク切換回路。[Claims for Utility Model Registration] A plurality of oscillation circuits each having a crystal oscillator, a buffer amplifier, and first and second switches that perform complementary operations in response to external control signals; Based on the operation of the first switch based on the supply, the clock signal from the buffer amplifier is outputted via the first switch, and the operation of the buffer amplifier is stopped to oscillate based on the operation of the second switch. A clock switching circuit characterized by stopping circuit operation.
JP6137090U 1990-06-12 1990-06-12 Pending JPH0420662U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6137090U JPH0420662U (en) 1990-06-12 1990-06-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6137090U JPH0420662U (en) 1990-06-12 1990-06-12

Publications (1)

Publication Number Publication Date
JPH0420662U true JPH0420662U (en) 1992-02-20

Family

ID=31589561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6137090U Pending JPH0420662U (en) 1990-06-12 1990-06-12

Country Status (1)

Country Link
JP (1) JPH0420662U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015053577A (en) * 2013-09-06 2015-03-19 日本電波工業株式会社 Oscillator and method of manufacturing oscillator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58189871A (en) * 1982-04-30 1983-11-05 Sony Corp Digital signal reproducer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58189871A (en) * 1982-04-30 1983-11-05 Sony Corp Digital signal reproducer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015053577A (en) * 2013-09-06 2015-03-19 日本電波工業株式会社 Oscillator and method of manufacturing oscillator

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