JPH0473211U - - Google Patents
Info
- Publication number
- JPH0473211U JPH0473211U JP11253190U JP11253190U JPH0473211U JP H0473211 U JPH0473211 U JP H0473211U JP 11253190 U JP11253190 U JP 11253190U JP 11253190 U JP11253190 U JP 11253190U JP H0473211 U JPH0473211 U JP H0473211U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- load
- control circuit
- driven
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Control Of Voltage And Current In General (AREA)
Description
第１図は本考案による低消費電力制御回路の一
実施例を示すブロツク図である。
１１，１２〜１ｎ……発振器、２１，２２〜２
ｎ……分周回路、３１，３２〜３ｎ……スイツチ
ング回路（ＯＮ／ＯＦＦ回路）、４１，４２〜４
ｎ……制御回路、５１，５２〜５ｎ……負荷、６
……判別回路、１０１，１０２〜１０ｎ……信号
線、２０１，２０２〜２０ｎ……信号線、３０１
，３０２〜３０ｎ……信号線、４０１，４０２〜
４０ｎ……信号線、５０１，５０２〜５０ｎ……
信号線、６０１，６０２〜６０ｎ……信号線。
FIG. 1 is a block diagram showing an embodiment of a low power consumption control circuit according to the present invention. 11, 12-1n...Oscillator, 21, 22-2
n...Frequency dividing circuit, 31, 32-3n...Switching circuit (ON/OFF circuit), 41, 42-4
n...Control circuit, 51, 52-5n...Load, 6
...Discrimination circuit, 101, 102-10n... Signal line, 201, 202-20n... Signal line, 301
, 302~30n...Signal line, 401, 402~
40n...Signal line, 501,502~50n...
Signal line, 601, 602-60n...Signal line.
Claims (1)
クを出力する複数の発振器と、 この複数の発振器の出力をそれぞれ分周する複
数の分周回路と、 この分周回路の出力をそれぞれオン・オフ制御
する複数のスイツチング回路と、 このスイツチング回路の出力をそれぞれの負荷
へ送出する制御回路と、 この制御回路の出力を常に検知することにより
、前記制御回路に接続された負荷が駆動している
か否かを判別し、判別結果を前記スイツチング回
路へ出力して、前記負荷が駆動しているときは前
記スイツチング回路をオンにし、前記負荷が駆動
していないときは前記スイツチング回路をオフに
する判別回路とを具備したことを特徴とする低消
費電力制御回路。[Claims for Utility Model Registration] A plurality of oscillators each outputting a clock having a preset frequency, a plurality of frequency divider circuits that divide the outputs of the plurality of oscillators, and an output of the frequency divider circuit. A plurality of switching circuits each perform on/off control, a control circuit sends the output of this switching circuit to each load, and by constantly detecting the output of this control circuit, the load connected to the control circuit is driven. outputting the determination result to the switching circuit, turning on the switching circuit when the load is being driven, and turning off the switching circuit when the load is not being driven. A low power consumption control circuit characterized by comprising a discrimination circuit for
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11253190U JPH0473211U (en) | 1990-10-26 | 1990-10-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11253190U JPH0473211U (en) | 1990-10-26 | 1990-10-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0473211U true JPH0473211U (en) | 1992-06-26 |
Family
ID=31860040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11253190U Pending JPH0473211U (en) | 1990-10-26 | 1990-10-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0473211U (en) |
-
1990
- 1990-10-26 JP JP11253190U patent/JPH0473211U/ja active Pending