JPH0446722U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a timing generation circuit according to an embodiment of this invention, FIG. 2 is a circuit diagram showing a specific configuration example of the switching signal generation circuit in FIG. 1, and FIG. 4 is a schematic block diagram showing an outline of a conventional DAT system, and FIG. 5 is a circuit configuration diagram of a conventional timing generation circuit. In the figure, 6A...timing generation circuit, 7a, 7
b...Crystal oscillator, 8a, 8b...Oscillation circuit, 1
0... Selector, 11... Frequency dividing circuit, 12... Switching signal generation circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] A timing generation circuit comprising a plurality of oscillation means, a switching means for selectively switching and outputting the output of the oscillation means, and a frequency division means for dividing the output of the switching means to generate a timing signal, A selection signal and a reference signal for selecting the output of the oscillation means are input, and after the selection signal changes, the next oscillation means corresponding to the selection signal starts oscillating due to a signal change of the reference signal, and then 2. A timing generation circuit characterized in that the timing generation circuit further comprises switching signal generation means for stopping the previous oscillation of the oscillation means and controlling switching of the switching means based on a signal change of the reference signal.