JPH04206971A - Film semiconductor device - Google Patents

Abstract

PURPOSE:To dissolve the deviation of the output voltage of a film semiconductor device equipped with a CMOS inverter without sacrifying the transmission speed or without increasing the occupied area by doping the channel region of an n-type film transistor with p-type impurities. CONSTITUTION:This is a film semiconductor device, which is equipped with the CMOS inverter constituted by a pair of n-type and p-type film transistor elements 5 and 6, and the channel region of the n-type film transistor 5 is doped with p-type impurities. Generally, in the TFT, where Polycrystal silicon is used for a channel layer, the driving capacity of an n-type TFT is larger than the driving capacity of a p-type TFT. But, if p-type impurities are implanted into the channel region of TFT 5, the inverse threshold voltage of the n-type TFT becomes high, so it decreases the difference with the driving force of the p-type TFT 6, and between the n-type TFT 5 and p-type TFT 6, the balance on transistor properties can be taken. Hereby, the output properties of the CMOS inverter constituted of a pair of n-type TFT 5 and p-type TFT can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a thin film semiconductor device, and particularly to a thin film semiconductor device suitable for driving a liquid crystal display element.

(Prior Art) Research and practical application of active matrix liquid crystal display devices in which a thin film transistor element (TPT) or a switching element is provided in a portion corresponding to each pixel in a liquid crystal panel is progressing.

Furthermore, together with the above-mentioned TPTs, TPTs that constitute a drive circuit (driver) for driving those TPTs,
Research is also progressing into a display device with an integrated drive circuit formed directly on the substrate of a liquid crystal display panel.

The minimum structural unit of a drive circuit for a liquid crystal display device is an inverter. An inverter having a CMO3 structure (CMOS inverter) is composed of a pair of n-type TFT and p-type TFT.

As the TPT, a TPT (polycrystalline silicon TFT) whose semiconductor layer is made of polycrystalline silicon is usually used. The reason is that polycrystalline silicon has higher electron and hole mobility than amorphous silicon, and
Since n-type and p-type TPTs can be created by the same process, it is easy to construct a CMO3 structure.

The CMO 3 made of polycrystalline silicon TPT having such properties is therefore excellent in terms of operating frequency characteristics and power consumption.

An example of a conventional CMOS inverter is shown in FIG.

Terminal 33 is the input terminal of the inverter, and terminal 34 is the output terminal of the inverter. In addition, the terminal 31 has a potential at a lower level of binary logic (hereinafter referred to as Lm level), or
A higher level potential (hereinafter referred to as LI potential) is applied to the terminal 32.

The terminal 31 to which the L potential is applied is connected to the source of the n-type TPT 35 through the contact hole 39, and is connected to the source of the n-type TPT 35.
The drain of the PT 35 is connected to the output terminal 34 of the inverter through a contact hole 40. Also, I(
The terminal 32 to which a potential is applied is connected to the source of the p-type TPT 36 through the contact hole 42, and is connected to the source of the p-type TPT 36 through the contact hole 42.
The drain of PT36 is connected to the output terminal 34 of the inverter through a contact hole 41. The input terminal 33 of the inverter is connected to both T through the contact hole 43.
Connected to gate electrodes 37, 38 of FT 35, 36.

The potential of the output terminal 34 of this inverter is determined by the difference between the potential of the terminal 31 and the potential of the terminal 32, and the ratio of the source-drain resistances of both TFTs 35 and 36. That is, when the potential of the input terminal 33 is L, the n-type TPT 35 is off, while the p-type TPT is on, and the resistance of the p-type TFT 36 is greater than the resistance of the n-type TFT 35. Low enough. Therefore, the voltage H at the terminal 32 is output to the output terminal 34. Conversely, when the potential of the input terminal 33 is H, the n-type TFT 35 is turned on, the p-type TFT 36 is turned off, and approximately Lm is outputted to the output terminal 34.

(Problems to be Solved by the Invention) Generally, in a TPT using polycrystalline silicon for the channel layer, the driving ability of an n-type TPT is greater than that of a p-type TPT. Therefore, when a CMOS inverter as described above is constructed using polycrystalline silicon TFTs, an n-type TFT
Since the resistance of PT is lower, the output of the inverter is VI
Inversion occurs in the region where N is low.

An example of such unbalanced inverter characteristics is shown in the third example.
Shown in the figure as a solid line. Here, a case is shown in which the input voltage VIN and the output potential V0IJT are both referenced to the L level, and the potential difference VHL between the H level and the L level is 20V. Since the characteristics of n-type TPT and those of p-type TPT are not symmetrical, the curve showing the output voltage ■01JT is VI
Regarding N, it is biased towards the L level side. If the output voltage V OUT is unbalanced in this way, it will cause a decrease in the operating speed and malfunction of the inverter.

The output voltage V OUT of the inverter is the potential difference VHL,
It is determined by the resistance ratio of the n-type and p-type TPTs that constitute the inverter. In order to improve the above-mentioned bias in the output voltage VOUT, it is conceivable to equalize the resistance ratio of both TPTs by changing the channel length and channel width of each TPT. For example, in the above inverter, the H side (p
In order to equalize the resistance ratio of the H-side (n-type TFT 36) and the H-side (n-type TFT 35), the channel width of the p-type TFT 36 must be set to n.
Make it larger than the channel width of the type TF T 35, or
Or, change the channel length of nQ TPT35 to p-type TPT
The channel length must be greater than 36.

However, such a method has problems in that it reduces the transmission speed of the inverter and increases the area of the inverter.

The present invention has been made to solve these problems, and its purpose is to eliminate the bias in the output voltage without sacrificing the transmission speed or increasing the occupied area. An object of the present invention is to provide a thin film semiconductor device equipped with a CMOS inverter that eliminates the problem.

(Means for Solving the Problems) A thin film semiconductor device of the present invention is a thin film semiconductor device including a CMOS inverter constituted by a pair of n-type and p-type thin film transistor elements, the thin film semiconductor device having a channel of the n-type thin film transistor. The above object is achieved by doping the region with a p-type impurity.

Further, it is preferable that the gate electrode of at least one type of thin film transistor element among the thin film transistors has a plurality of gate electrode portions spaced apart in the channel length direction.

Further, the channel region of the thin film transistor element having the plurality of gate electrode parts has a plurality of channel region parts arranged at intervals in the channel length direction, and each of the channel region parts is a part of the thin film transistor element. facing each of the gate electrode portions via a gate insulating film,
The region sandwiched between the channel region portions is preferably of the same conductivity type as the source region and drain region of the thin film transistor element.

Furthermore, the channel region of the p-type thin film transistor may also be doped with a p-type impurity.

Also, the dose amount of the p-type impurity is lXl0"Cm-2
It is preferable that it is above and 5×10 12 cm −2 or less.

Furthermore, the semiconductor layers of the AAN type and P type thin film transistors may be polycrystalline silicon layers.

In general, in a TPT using polycrystalline material for the channel layer, the driving ability of an n-type TPT is greater than that of a p-type TPT. However, if a p-type impurity is implanted into the channel region of the TPT, the inversion threshold voltage of the n-type TFT increases, so that the difference between the driving force and the p-type TFT can be reduced. In this way, the transistor characteristics can be balanced between the n-type TFT and the p-type TFT. Therefore, the output characteristics of the CMOS inverter formed by a pair of n-type TFT and p-type TFT are improved.

Furthermore, by dividing the game MIS pole and channel region into a plurality of parts, a plurality of junctions are formed between the source and the drain. Therefore, even if a high voltage is applied between the source and the drain, the voltage applied to one junction is reduced, thereby suppressing the occurrence of junction leakage current. Therefore, even when a high voltage is applied, the off-resistance of the TPT does not decrease, and deterioration of the output characteristics of the CMOS inverter is suppressed.

(Example) The invention will now be described with reference to examples.

FIG. 1 shows an example of the planar structure of the CMOS inverter of the thin film semiconductor device of this embodiment.

The main difference from the conventional CMOS inverter shown in FIG. 4 is that in this embodiment, p-type impurities are implanted into the channel region of the n-type TFT 5,
The reason is that the gate electrode is divided into two.

FIG. 2 shows a cross-sectional structure taken along line AA' in FIG. 1.

The configuration of this embodiment will be explained below in accordance with the manufacturing process with reference to FIG.

First, a polycrystalline silicon thin film of 80 nm is deposited on the entire surface of a transparent insulating substrate 15 made of glass, quartz, etc. using the CVD method.
Form with a thickness of . This polycrystalline silicon thin film was later
channel region 16 of type TFT 5, source fiJ region (source electrode) 25, drain region (drain electrode) 26, channel region 16, and channel region 30 of p-type TFT 6
, a source region (source electrode) 28, and a drain region (drain electrode) 27.

After S1+ ions are implanted into this polycrystalline silicon thin film to make it amorphous, it is annealed in a nitrogen atmosphere to obtain a polycrystalline silicon thin film having a large crystal grain size.

In addition to the above-mentioned insulating transparent substrate, as a substrate,
A structure in which an insulating film is formed on a semiconductor substrate can also be used.

Next, the polycrystalline silicon thin film was patterned into polycrystalline silicon thin films 50 and 60 having rectangular shapes as shown in FIG. The channel widths of the n-type TFT 5 and the p-type TFT 6 are determined in consideration of the driving capability required of the inverter, and in this embodiment, they are set to 20 μm.

Next, a photoresist was applied, and by exposure and development steps, the photoresist was patterned into a shape having an opening only in the region 14 surrounded by the dotted line in FIG. After this, region 1 of the polycrystalline silicon thin film is
Only No. 4 was doped with a p-type impurity such as boron.

The dose amount was 5×],012 cm−2 or less. By changing this dose amount, the threshold voltage of the n-type TFT 5 can be set to an arbitrary value. However, the effect of controlling the threshold voltage cannot be achieved unless at least 1xlollcm-'' or more is implanted.

After removing the photoresist, an oxide film 17 to be a gate insulating film was formed to a thickness of 1100 nm by CVD. The oxide film 17 can also be formed by sputtering or by thermally oxidizing the upper surface of the polycrystalline silicon thin film. Further, the doping of the region 4 of the two series of n-type TFTs 5 can also be performed by ion implantation after the gate oxide film 17 is formed.

Next, a polycrystalline silicon thin film was formed by a CVD method, and impurities (dopants) were doped by a diffusion method to lower the resistance. This doping can also be performed by ion implantation.

In this example, the thickness of this polycrystalline silicon thin film is 450 mm.
It was set as nm.

By patterning this polycrystalline silicon thin film, the goo 1 electrodes 7.8 of both TFTs 5.6 were formed. n
The gate electrode 7 of the type TFT 5 was patterned into a shape having two gate electrode portions 7a and 7b. The two gate electrode portions 7a and 7b are spaced apart in the channel length direction.

The width (length in the channel length direction) of each gate electrode portion 7a or 7b was 4 μm (total 8 μm). In addition, p-type TF
The width of the gate electrode of T6 was 8 μm.

The gate electrode wiring extending from the input terminal 3 is branched in the middle so that the same voltage is applied to the two gate electrode portions 7a and 7b of the n-type TFT 5. However, the shape of the gate electrode 7 does not necessarily have to be divided into branch-like parts, and each branch-like gate electrode part 7a
and 7b may be connected to each other outside the channel region. Furthermore, the gate electrode 7 has a structure in which it is completely divided into independent gate electrode portions 7a and 7b, which are electrically connected to each other by wiring such as AI formed through an insulating film. Good too.

Next, in the semiconductor layer, the source region 2 of the n-type TFT 5
5, drain region 26 and two gate electrode portions 7a
and 7b was doped with an n-type impurity by ion implantation. This ion implantation was performed using gate electrode portions 7a and 7b as masks. Due to this ion implantation, the child region 16 of the n-type TFT 5 is formed by two regions spaced apart in the channel length direction.
It was divided into two channel area parts 1.6a and 161). Further, since the region 29 is formed in a self-aligned manner in the same manner as the formation of the source region 25 and the drain region 26, each of the channel region portions 16a and 16b is connected to the gate electrode portions 7a and 7b via the gate insulating film 17. are arranged so as to face each of them.

The region 29 formed in this way is the source region 25
and the same conductivity type as the drain region 26. On the other hand, since channel region portions 16a and 16b were not doped with n-type impurities, a junction was formed between region 29 and channel region portions 16a and 16b.

Next, in the semiconductor layer, the source region 2 of the p-type TFT 6 is
8 and the drain region 27 were doped with p-type impurities by performing ion implantation using the gate electrode 8 as a mask.

Note that when performing ion implantation to form the source and drain of the n-type TFT 5, a resist covering the portion where the p-type TFT 6 is to be formed is formed as an implantation mask, and the p-type TFT 6 is formed as an implantation mask.
When performing ion implantation to form the source and drain of the type TFT 6, a resist was formed as an implantation mask to cover the portion where the n-type TFT 5 was to be formed.

Next, a silicon oxide film or a silicon nitride film with a thickness of 700 nm was formed on the entire surface of the substrate by the CVD method to form an insulating layer 20.

Next, contact holes 9, 10, . . . are placed at the positions shown in FIG.
11, 12 and 13 were formed. As shown in Figure 2,
The contact holes 9, 10, 11 and 12 are formed in the insulating layer 2.
0 and the gate insulating film 17 described above.

Further, the contact hole 13 of the input terminal is formed in the insulating layer 20.
was formed through the

Next, the L potential supply terminal 1, the H potential supply terminal 2, the input terminal 3, and the output terminal 4 were formed of a low resistance metal film such as AI. Terminal 1 is connected to n-type TFT through contact hole 9.
The source region 25 of No. 5 is connected to the source region 25 of No. 5. Terminal 2 was connected to source region 28 of p-type TFT 6 through contact hole 12, and terminal 3 was connected to p-type and gate electrode 7.8 of p-type TFT 5.6 through contact hole 13.

In addition, terminal 4 is connected to p through contact hole 10.11.
type and p-type TPT drain regions 26,27.

The characteristics of the n-type TFT 5 of this example are shown in FIG.
FIG. 6 shows the characteristics of the conventional n-type TFT 35 shown in the figure.

Further, the characteristics of the present embodiment and the conventional p-type TFT 6.36 (the structures of both are exactly the same) are shown in FIG.

Comparing the characteristic lines in FIG. 5 and FIG. 6, it is found that the n-type T of the present invention
It can be seen that the resistance of the FT5 is higher and the drain current (TD) level is lower than that of the conventional one. This is because the inversion dark value voltage of the n-type TFT 5 is increased by implanting p-type impurities into the channel region.

Comparing the characteristics of the p-type TFT described above and the characteristics of the p-type TFT6.36 shown in FIGS. It turns out that it is excellent.

In FIG. 3, the dotted line shows the transfer characteristic when VHL=20V of the CMOS inverter of the thin film semiconductor device of this example.

When compared with the transfer characteristics of the conventional CMOS inverter shown by the solid line in the figure, it can be seen that the symmetry between the H side and the L side is good.

In this example, the channel widths of the pair of p-type and p-type TFTs 5.6 constituting the CMOS inverter were set to be equal, but in order to further improve the symmetry of the characteristics of the n-type TFT 5 and p-type TFT 6, It is also possible to adjust the imbalance in driving ability between the two by changing the channel width.

Further, in this embodiment, the channel lengths of both TFTs 5.6 are set to be the same, but this can also be changed. In this way, by independently determining the channel length and channel width of the n-type TFT 5 and the p-type TFT 6 to appropriate values, the inverter characteristics can be further improved.

Further, in this embodiment, the gate electrode 7 of the n-type TFT 5 is divided into two parts, but it can also be divided into a larger number of parts. In this case, the voltage applied between the source and drain is divided into more junction resistances, so the withstand voltage between the source and drain is further improved.
CMO that can operate normally even at higher voltages
It can be an S inverter.

In this embodiment, of the pair of TPTs constituting the CMOS inverter, only the gate electrode 7 of the p-type TPT 5 is made into a split shape, or the gate electrode 8 of the p-type TFT 6 may be made into a split shape. . In this case, p-type TFT6
Also, the withstand voltage characteristics between the source and drain are improved, and even better inverter characteristics can be obtained.

In the embodiment described above, ion implantation into the channel region for controlling the threshold voltage is performed only in the channel region of the n-type TFT 5, but not in the channel region of the p-type TFT 6. Also, by simultaneously implanting impurities into the channel regions of both TFTs 5.6, impurity regions can be provided in both TFTs 5.6. p-type TFT6 shown in FIG.
The characteristics of the p-type T F T are not significantly different from those of FIG.
The implantation into the channel region of No. 6 has almost no effect on the transistor characteristics. However, this process has the advantage that the step of forming a photoresist having an opening in region 14 can be omitted.

(Effects of the Invention) According to the thin film semiconductor device of the present invention, since the characteristics of the p-type and p-type thin film transistor elements constituting the CMOS inverter have good symmetry, the output voltage of the CMOS inverter is not biased. few.

Therefore, malfunctions of the thin film semiconductor device are less likely to occur.

Furthermore, since the above effects can be obtained without increasing the channel length or channel width of the thin film transistor element, there is no need to increase the element area and there is no reduction in transmission speed.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a CMOS inverter according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A' in FIG. O
Figure 4 is a plan view showing a conventional CMOS inverter, Figure 5 is a characteristic diagram of an n-type TFT that constitutes the CMOS inverter of the embodiment, and Figure 6 is a graph showing the transfer characteristics of a conventional CMOS inverter. configuring the CMOS inverter of
Figure 7 is a characteristic diagram of a p-type TFT without p-type impurity implanted into the channel region, and Figure 8 is a characteristic diagram of a p-type TFT with p-type impurity implanted into the channel region. be. ■, 31...L level potential terminal of CMOS inverter, 2.32...H level potential terminal, 3.33...
・Input terminal, 4.34... Output terminal, 5.35...
n-type TFT, 6.36-p-type TFT, 7.37...
Gate electrode of n-type TFT, 7a, 7b... Gate electrode portion, 8.38... Gate electrode of p-type TFT, 9-1
．． 3.39-43...contact hole, 15...
Substrate, 16... Channel region of n-type TFT, 16a1
16b... Channel region portion, 17... Gate insulating film, 20... Interlayer insulating film, 25... Source region of n-type TFT, 26... Drain region of n-type TFT, 27
...Drain region of p-type TFT, 28...p-type TF
Source region of T, 30... Channel region of p-type TFT. that's all

Claims (1)

[Claims] 1. A thin film semiconductor device equipped with a CMOS inverter constituted by a pair of n-type and p-type thin film transistor elements, wherein a channel region of the n-type thin film transistor is doped with a p-type impurity. thin film semiconductor devices. 2. The thin film semiconductor device according to claim 1, wherein the gate electrode of at least one type of thin film transistor element among the thin film transistors has a plurality of gate electrode portions spaced apart in the channel length direction. 3. The channel region of the thin film transistor element having the plurality of gate electrode portions has a plurality of channel region portions spaced apart in the channel length direction, and each of the channel region portions has a gate insulator of the thin film transistor element. 3. The thin film semiconductor device according to claim 2, wherein a region facing each of the gate electrode portions via a film and sandwiched between the channel region portions has the same conductivity type as a source region and a drain region of the thin film transistor element. 4. Also in the channel region of the p-type thin film transistor,
4. The thin film semiconductor device according to claim 1, wherein the thin film semiconductor device is doped with a p-type impurity.