JPH04207864A - Television monitor - Google Patents

Abstract

PURPOSE:To optionally adjust the delay of the vertical and horizontal synchronizing signals within a single cycle and therefore to accurately display an effective display screen by providing a horizontal position varying part where a horizontal synchronizing signal is set at an optional position within one horizontal cycle and a vertical position varying part where a vertical synchronizing signal is set at an optional position within one vertical cycle. CONSTITUTION:The picture signals R, G and B are separate from a horizontal synchronizing signal HD in a normal monitor. The signal HD is inputted to a memory circuit 8b of a horizontal position varying pert 11. A variable resistor 5b produces a signal 57 to show a delay degree of the signal HD with a signal SW2 which varies for adjustment of the position of the signal HD. Meanwhile a vertical synchronizing signal VD is inputted to a memory circuit 8a of a vertical position varying part 10. Then a variable resistor 5a produces a signal 51 to show a delay degree of the signal VD with a signal SW1 which varies for adjustment of the position of the signal VD.

Description

[Detailed description of the invention] [Industrial application fields] The present invention relates to television monitors.

[Prior Art] Generally, a television monitor is equipped with a sync separation circuit, and a given composite signal is processed by the sync separation circuit inside the monitor.
Separated into image signal, vertical synchronization signal and horizontal synchronization signal. Therefore, if synchronization and image signals conforming to the standards are provided to the television monitor, the effective display portion will be accurately displayed on the monitor screen as shown in FIG. 2(a). However, since the monitor itself has a margin of a few percent compared to the official standard, it will still be synchronized even if some non-standard synchronization is applied.

At this time, due to the difference in length between non-standard synchronization and standard horizontal and vertical blanking, as shown in Figure 2 (,b)
Part of the horizontal blanking period and vertical blanking period is displayed on the screen as shown in the following. In such a case, it is necessary to move the horizontal and vertical positions to display a normal, effective display screen.

Conventionally, the horizontal and vertical positions have been adjusted using a configuration as shown in FIG. In other words, the SW multiplication signal conversion circuit 2 that indicates the amount of vertical and horizontal position adjustment is manually input, and the conversion circuit 2 uses capacitors, resistors, transistors, etc.
A delay amount corresponding to the amount of the doubled signal is sent to the vertical synchronization circuit 1 and the horizontal synchronization circuit 3. The vertical synchronizing circuit 1 and the horizontal synchronizing circuit 3 each delay the VD signal and the HD signal by the amount of delay to form new synchronizing signals VDA and HDA to control the CRT 4.

[Problem to be solved by the invention] However, according to this conventional technology, the VD signal and the HD signal
Since the signal delay amount was directly supplied to the vertical synchronization circuit 1 and horizontal synchronization circuit 3 to control the vertical position and horizontal position,
The adjustment range cannot be widened.

Therefore, when a synchronization signal that significantly deviates from the standard is applied, there is a problem in that the vertical blanking and horizontal blanking portions on the screen cannot be completely erased.

[Means for Solving the Problems] A television monitor of the present invention includes a horizontal position variable section that sets a horizontal synchronization signal at an arbitrary position within one horizontal period, and a vertical synchronization signal at an arbitrary position within one vertical period. It is equipped with a vertical position variable section for setting.

[Example code] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The present embodiment is a digital color television monitor (that is, a digital television receiver), and is composed of a vertical position variable section 10, a horizontal position variable section 11, and a general color television monitor, or in the figure, a general color television monitor. Only the CRT4 is shown in the section. The horizontal position variable section 11 includes a variable resistor 5b, a conversion circuit 2b, a control circuit 6b, a reset circuit 7b, and a memory circuit 8b. Now, when the states of FIGS. 2(a) and 2(b) are displayed as waveforms in one horizontal period, they become as shown in the signals (a) and (b) of FIG. 3. In other words, the length of water level synchronization and water level blanking is m for signal (a), but n for signal (b), and in signal (b), a horizontal blanking mark extends over the image part of signal (a). It turns out. In a normal monitor, the image signal RGB and the horizontal synchronization signal HD shown in FIG. 3 are separated.

The horizontal synchronization signal HD is input to the memory circuit 8b of the horizontal position variable section 11. In addition, in the variable resistor 5b, the signal SW2 is changed to adjust the horizontal synchronizing signal position.
A signal 57 indicating how much to delay the horizontal synchronization signal HD is generated. The signal 57 is input to the conversion circuit 2b, which generates a signal 58 which becomes the read start address of the memory circuit 8b and supplies it to the control circuit 6b. The control circuit 6b generates and enters a write signal, a write address 60, and a read address 61 to the memory circuit 8b. Now, the number of samples between -horizontal periods is 500 as an example.
(0 to 499), the horizontal synchronizing signal (D) is stored in the memory circuit 8b by the write address 60 as shown in FIG.

The reset circuit 7b looks at the write address 60 and generates a reset signal 59 to the control circuit 6b so that the write address 60 becomes constant in one horizontal cycle from 0 to 499.

Suppose now that the horizontal blanking on the screen has been adjusted to be erased, and the value of the signal 58 when set to the best condition is 430 as shown in FIG. 3, for example. At this time, the control circuit 6b sets the beginning of the read address 61 to 430 and counts in order. The memory circuit 8b has addresses 0 to 2.
Since the horizontal synchronization part is stored in address 9, the read address 61 becomes 499 and returns to O after being reset, so that the new horizontal synchronization signal HDA is accurately reproduced as shown in FIG. In this way, a new horizontal synchronization signal HDA can be obtained in which the horizontal synchronization signal can be moved arbitrarily within the horizontal period.

For explanation, using this signal HDA, image signal R-G
When viewed as a composite signal together with -B, it becomes a signal (b') in FIG. 3, in which the horizontal blanking length has been changed to m'. This value m' is the value (
Since it is approximately equal to m), the effective display area in the horizontal direction is accurately displayed on the screen.

Next, the vertical position variable section 10 will be explained. The configuration includes a variable resistor 5a, a conversion circuit 2a, a control circuit 6a, a reset circuit 7a, a memory circuit 8a, and a register 9.

The vertical synchronization signal VD is sent to the memory circuit 8 of the vertical position variable section 10.
input to a. Further, the variable resistor 5a generates a signal 51 indicating how much the vertical synchronizing signal VD is to be delayed in response to the signal SWI which changes to adjust the position of the vertical synchronizing signal. The signal 51 is input to the conversion circuit 2a, which generates a signal 52 which becomes the read start address of the memory circuit 8a, and supplies it to the control circuit 6a. Control circuit 6
On the other hand, the write signal and write address 54 of the memory circuit 8a are generated by the signal HD from the horizontal position variable section 11.
, a read address 55 is generated. Now, let us take the number of samples between -vertical periods as an example.

600 (0 to 599), the vertical synchronizing signal VD is stored in the memory circuit 8a using the write address 54, as shown in FIG. The reset circuit 7a monitors the write address 54 and generates a reset signal 53 to the control circuit 6a so that the write address 54 becomes one vertical period O to 599, thereby making it constant. Now, the value of signal 52 when adjusted to erase the vertical blanking on the screen and set to the best condition is 5 as shown in Figure 4.
Let's say it was 70. At this time, the control circuit 6a sets the beginning of the read address 55 to 570 and counts in order. Since the vertical synchronization part is stored in the memory circuit 8a from addresses O to 1, the read address 55 becomes 599 and returns to 0 after being reset, so the new vertical synchronization signal VDA is accurate as shown in FIG. will be reproduced in

However, the signal 56 from the memory circuit 8a is horizontally synchronized HD.
Since it is synchronized with the signal HDA from the horizontal position variable section 11 by the register 9, it is output as the new vertical synchronization signal VDA. As a result, the effective display screen in the vertical direction is accurately displayed on the screen.

In the CRT4, the image signal R-G-B and the new vertical synchronization signal V
The image is displayed under the control of DA and the new horizontal synchronization signal HDA. The memory circuits 8a and 8b can be composed of general static RAM, and the control sections 6a and 6b can be composed of a counter and a ROM.

Although the embodiments described above are digital color television monitors, the present invention can be applied to analog television monitors. In the case of an analog system, in the vertical position variable section 10 and the horizontal position variable section 11, D/A and A/D converters are used for the vertical synchronization signals VD, VDA, and horizontal synchronization signals HD, HDA, or the scale is large. However, it can be realized by configuring everything with analog circuits.

Further, although FIG. 1 shows a detailed block diagram of the vertical position variable section 10 and the horizontal position variable section 11, the position variable section in the present invention is not limited to the system of the embodiment, and various modifications are possible.

[Effects of the Invention] As explained above, according to the present invention, since the vertical and horizontal position variable parts are provided, even if a non-standard horizontal synchronization signal is applied, the synchronization can be performed within the synchronization pull-in range of the monitor. By arbitrarily adjusting the delay of the vertical and horizontal synchronizing signals within one cycle, an effective display screen can be displayed accurately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a front view showing an image on a monitor to explain the problem to be solved by the present invention, and FIGS. 3 and 4 are A signal waveform diagram for explaining the operation of one embodiment, and FIG. 5 is a block diagram of a conventional example. 1...Vertical synchronization circuit, 2...Conversion circuit, 3...Horizontal synchronization circuit, 4...◆...Conflict/CRT. 5...... Variable resistor, 6... Control circuit, 7... Reset circuit, 8... Memory circuit, 9 ········register. Patent applicant: NEC Corporation

Claims (1)

[Claims] A television monitor comprising: a horizontal position variable section that sets a horizontal synchronization signal at an arbitrary position within one horizontal cycle; and a vertical position variable section that sets a vertical synchronization signal at an arbitrary position within one vertical cycle. .