JPH04209035A - Artificial trouble generating circuit - Google Patents

Abstract

PURPOSE:To facilitate a diagnosis of a trouble recovering function by causing artificial trouble in a specific operation state of a device and also generating exactly the same artificial trouble. CONSTITUTION:For the generation of the artificial trouble in the specific operation state of the device, the address of a specific microinstruction to generate the artificial trouble is set in a register 4 which prescribes the artificial trouble address. A comparing circuit 5 compares a next execution address signal 200 with the address set in the register 4 and generates an artificial trouble generation signal 500 when the both match each other. An artificial trouble generator 6 generates the artificial trouble according to the artificial trouble generation signal 500. Thus, the artificial trouble is generated aiming at the specific address of the microinstruction.

Description

[Detailed description of the invention]

[00011

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo failure generating circuit for a data processing device. [0002] BACKGROUND OF THE INVENTION In recent years, as the field of application of electronic computers has expanded dramatically, the demand for high reliability of systems has been increasing year by year. For this reason, computers have come to be equipped with a failure recovery function. [0003] However, it is also necessary to consider the reliability of the failure recovery function itself, and in order to diagnose this failure recovery function, it is necessary to consider the reliability of the failure recovery function itself. It may have a built-in fault circuit. Conventionally, such a fault generating circuit has used a method of generating a pseudo fault regardless of the operating state of the device. [0004]

[Problems to be Solved by the Invention] The above-mentioned conventional pseudo-fault generating circuit randomly generates pseudo-faults regardless of the operating state of the device. Another drawback is that it is difficult to generate a pseudo fault targeting a specific phase, and at the same time, it is difficult to repeatedly generate the same pseudo fault. [0005]

[Means for Solving the Problems] The pseudo-failure generation circuit of the present invention includes a control memory that stores a microprogram composed of microinstructions, and a microinstruction that stores a microinstruction containing a next execution address read from the control memory. A register, a suspected failure address register that holds the address of the specific microinstruction that caused the failure, the next execution address of the microinstruction stored in the microinstruction register, and the address held in the doubtful failure address register. and a false fault generator that generates a false fault when the comparison results match. [0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment of the present invention. [00071] Referring to FIG. 1, this embodiment includes a control memory 1, a microinstruction register 2, a decoder 3, a register 4 for defining a pseudo-fault address, a comparison circuit 5, and a pseudo-fault generator 6. [00081 The microinstructions constituting the microprogram stored in the control memory 1 are stored in the microinstruction register 2 when read out. A part of the microinstruction stored in the microinstruction register 2 is decoded by the decoder 3 and becomes a control signal 300 for executing the microinstruction. On the other hand, part of the microinstructions stored in the microinstruction register 2 becomes the next execution address signal 200, specifies the address on the control memory 1, and stores the next microinstruction in the microinstruction register 2. This series of operations forms a microinstruction execution sequence. [0009] When it is desired to cause a pseudo fault to occur in a specific operating state of the device, the address of a specific microinstruction for which a pseudo fault is to occur is set in the register 4 that defines the pseudo fault occurrence address. Comparison circuit 5 receives next execution address signal 2
00 and the address set in the register 4 that defines the pseudo-fault address, and if the two match, a pseudo-fault occurrence signal 500 is issued. This false fault occurrence signal 50
0, the pseudo fault generator 6 generates a pseudo fault. In this way, it is possible to generate a false fault by targeting a specific address of a microinstruction. [00101] [Effects of the Invention] According to the present invention, it is possible to generate a pseudo fault in a specific operating state of the device, and the same pseudo fault can be repeatedly generated, making it easy to diagnose the fault recovery function. There is a certain effect.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention.

[Explanation of symbols]

1 Control memory 2 Microinstruction address 3 Decoder 4 Register 5 that specifies the pseudo-fault occurrence address Comparison circuit 6 pseudo-fault generator

[Figure 1]

Claims (1)

[Claims] 1. A control memory that stores a microprogram composed of microinstructions, a microinstruction register that stores microinstructions including a next execution address read from the control memory, and a microinstruction register that stores a specific microinstruction that causes a pseudo failure. a pseudo fault occurrence address register that holds an address; a comparison circuit that compares the next execution address in the microinstruction stored in the microinstruction register with the address held in the pseudo fault occurrence address register;
1. A pseudo-fault generating circuit comprising: a pseudo-fault generator that generates a pseudo-fault when a match is found as a result of comparison.