JPH0421348B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention is a semiconductor RAM (random access RAM).
memory).

FIG. 1 shows a memory cell conventionally used in CMOSRAM. P channel transistor 3,
4, and BIT, which is a data input/output line, through an N-channel transistor (transfer gate) whose ON/OFF is controlled by an address line ADR to a flip-flop formed by a loop connection of an inverter consisting of N-channel transistors 5 and 6; It is connected to the. When the memory cell is in a read state, a signal is transmitted from the flip-flop to the data line, and in a write state, a signal is transmitted from the data line to the flip-flop when the transfer gate is turned on. A feature of this CMOS memory cell is that in a stable state, the inverter that makes up the flip-flop requires very little power because it is CMOS, and therefore almost no power is required to hold the data stored in the memory. It consumes less power and consumes less power than N-MOS when in operation, so it is used in a wide variety of applications due to its low power operation.

On the other hand, a drawback of this CMOS memory is that its cell size is large, and therefore the memory capacity stored on the same chip size is smaller than that of an N-MOS RAM, making it difficult to increase the capacity. The root cause of this is that since it is CMOS, there is a space to create a P-channel transistor on a plane, and a P ^- well that insulates the N-channel and serves as a substrate.
The reason is that a separate space is required.

The present invention uses a flip-flop formed by cross-connecting the input and output of two inverters as a memory cell, and has a data line for inputting and outputting data between the memory cell and the random access memory. The purpose is to reduce the size.

FIG. 2a shows an example of a planar pattern of a memory cell according to the present invention, and FIG. 2b shows a cross-sectional view of AB. The embodiments of the present invention will be described based on an example in which a polycrystalline silicon film serving as a load element is formed as a P-channel thin film transistor. Selective oxidation mask boundary 1
There is a portion within 8 that will become a source/drain region. After forming a field film by selective oxidation, growing a gate oxide film, and opening contact holes 10 and 11 for connecting the first layer of polycrystalline silicon and the substrate 30, the first layer of polycrystalline silicon is grown. After depositing patterns 19, 20, 21, and 27 (shaded patterns), P ions are implanted into the entire surface to form sources/drains 31, 32, and 33. Thereafter, the second field film 36 is deposited, the second field film on the polycrystalline silicon 19, 20 that will become the gate is removed, and the polycrystalline silicon 19, 20 is thermally oxidized to form a gate insulating film of the thin film transistor. . After that, contact hole 1 connects the first layer and the second layer of polycrystalline silicon.
A second layer of polycrystalline silicon 22, 23 (pattern of dots) with holes 2, 13, and 14 formed to form the channel, source, and drain of the thin film transistor.
is deposited and selectively diffused with P ⁺ . Furthermore, after depositing the third field film 35 and opening the contact holes 15, 16, 17, Al
- Forming Si layers 24, 25, 26. 24, 25
is a data line, and 26 is a power line. This result N ⁺
A source connected to the (-) power supply V _SS of the diffusion layer 31;
32 as a drain, polycrystalline silicon 20 as a gate, a source 55 connected to the (+) power supply _VDD in the polycrystalline silicon layer 22, a channel 54, a drain 56, and a P channel transistor as a gate with polycrystalline silicon 20. A CMOS inverter can be configured in which channel transistors are formed and each drain is connected via a diode.
P formed in polycrystalline silicon 22, 23
The arrangement direction of the source region, channel region, and drain region of the channel transistor is the same as that of the data line 2.
4, 25 in the extending direction.

FIG. 5 shows a circuit diagram of the cell pattern shown in FIG. 2. N-channel transistors 40 to 43 are formed in bulk silicon single crystal, P-channel transistors 44 and 45 are formed as polycrystalline thin film transistors, and diodes 46 and 47 are formed at the connection point of the polycrystalline silicon of the P-channel and N-channel transistors. This diode does not interfere with the operation of the memory.

The feature of the present invention is as shown in Fig. 2b.
When configuring an inverter, a method is used in which one gate electrode is used in common, an N-channel transistor is placed below the gate electrode, a P-channel transistor is placed above the gate electrode, and the drains are connected together. Since the P-channel and N-channel regions, which were conventionally arranged in a plane, are arranged in three dimensions, the cell size is dramatically reduced, and the memory capacity with the same chip size increases rapidly.

In general, polycrystalline silicon layers have extremely low mobility and poor transistor characteristics compared to single-crystalline silicon, and are known to have particularly high OFF leakage. However, as a result of our efforts to improve this characteristic, the inventors discovered the following. As shown in Figure 3, mobility is improved when the deposition temperature of polycrystalline silicon is lower than 700°C, especially around 500°C.
Characteristics close to those were obtained. In addition, improving OFF leakage depends on the manufacturing method of the gate film, which is made by thermally oxidizing polycrystalline silicon, and dry oxidation at high temperature is the best method. Furthermore, even if the deposition temperature of the polycrystalline silicon layer is high, the mobility and OFF leakage can be improved by performing laser annealing.

Figure 4 shows a memory cell of the same size as that used in a memory cell obtained by depositing polycrystalline silicon at 500°C, then light-doping P ions into the channel by ion implantation, and forming a gate oxide film at 1100°C. Shows the characteristics of a transistor. The properties are sufficient for memory applications.

In the present invention, a thin film transistor serving as a load element of an inverter constituting a memory cell is arranged above a transistor having a source and a drain region formed apart from each other across a channel region on the surface of a substrate, and By setting the arrangement direction of the region, channel region, and drain region to be the extending direction of the data line, the spacing between the data lines can be determined regardless of the length of the channel region of the thin film transistor, which enables random access with a high degree of integration.・It is possible to obtain a memory that is approximately half the size of a conventional cell configured using the same design rules, and the 5 μm rule was previously limited to 4 Kbit, but with the implementation of this invention, 16 Kbit is now within reach. It became.

[Brief explanation of drawings]

FIG. 1 is a cell diagram of a MOSRAM. Figure 2a
2 is a plan view of a CMOSRAM according to the present invention, and FIG. 2b shows a cross-sectional view. FIG. 3 is a diagram showing the relationship between the mobility of polycrystalline silicon and the deposition temperature, and FIG. 4 is a diagram showing the characteristics of a polycrystalline silicon transistor obtained according to the present invention. FIG. 5 is a circuit diagram of FIG. 2.

Claims (1)

[Scope of Claims] 1. A random access memory that uses a flip-flop formed by cross-connecting the input and output of two inverters as a memory cell, and has a data line for inputting and outputting data between the memory cell and the memory cell. Each of the inverters is composed of first and second transistors connected in series between power supplies, and the first transistor has a source and a drain region formed on the surface of the substrate and spaced apart from each other with a channel region in between. The second transistor is a thin film transistor formed above the substrate and spaced apart from each other with a channel region in between, and has a source and drain region made of a silicon layer, and the source region, the channel region, A random access memory characterized in that the direction in which the drain region is arranged is the direction in which the data line extends.