JPH0459784B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention is a CMOS (complementary MOS transistor)
This relates to semiconductor RAM (random access memory) using

FIG. 1 shows a memory cell conventionally used in CMOSRAM. P channel transistor 3,
4, and a flip-flop formed by a loop connection of an inverter consisting of N-channel transistors 5 and 6, data is input/output via N-channel transistors (transfer gates) 1 and 2 whose ON/OFF is controlled by an address line ADR.
BIT, and are connected. When the memory cell is in the read state, the signal is transferred from the flip-flop to the data line, and in the write state, the signal is transferred from the data line to the flip-flop.
Communicate when turned ON. A feature of this CMOS memory cell is that in a stable state, the inverter that makes up the flip-flop requires very little power because it is CMOS, so it requires very little power to retain the data stored in the memory. It consumes less power than N-MOS, and even in the operating state, it consumes less power than N-MOS, and because of its low power operation, it is used in a wide variety of fields.

On the other hand, the disadvantage of this CMOS memory is that its cell size is large, and therefore N-MOS
Compared to RAM, the memory capacity stored on the same chip size is small, making it difficult to increase the capacity. The root cause of this is that, since it is CMOS, space is required to create a P-channel transistor in a plane, and space to create and separate a P ^- well that insulates the N-channel and serves as a substrate.

The present invention uses a flip-flop formed by cross-connecting the input and output of two inverters as a memory cell, and has a data line for inputting and outputting data between the memory cell and the random access memory. - The purpose is to reduce the cell size and to prevent thin film transistors from being affected by data lines.

The present invention solves the above problems by:
A memory cell is formed by cross-connecting the input and output of two inverters each having a MOS transistor and a thin film transistor connected in series between power supplies, and is formed on the substrate surface and above the substrate. In the random access memory having a data line for transmitting data, the MOS type transistor has a source and drain region formed on the surface of the substrate and spaced apart from each other with a channel region in between, and the thin film transistor has a Source and drain regions are formed in a silicon layer disposed above the substrate and spaced apart from each other with a channel region in between, and the data line is formed on one surface of the silicon layer portion forming the channel region of the thin film transistor. This is characterized in that an insulating film that is thicker than the gate insulating film is interposed above the silicon layer portion.

FIG. 2a shows a planar pattern of an embodiment of the random access memory according to the present invention, and FIG. 2b shows a cross-sectional view taken along line AB in FIG. 2a.
There are portions that will become source/drain regions within the boundary 18 of the selective oxidation mask. After forming a field film by selective oxidation, growing a gate oxide film and forming contact holes 10 and 11 for connecting the first layer of polycrystalline silicon and the substrate 30, the first layer of polycrystalline silicon is grown. Crystalline silicon 19, 20,
After depositing patterns 21 and 27 (hatched patterns), P ions are implanted over the entire surface to form the source.
Drains 31, 32, and 33 are formed. After this,
A second field film 36 is deposited, and the second field film on the polycrystalline silicon 19, 20 that will become the gate is removed.
The top is thermally oxidized to form a gate insulating film of a thin film transistor. After that, contact holes 12 and 1 connecting the first layer and the second layer of polycrystalline silicon are formed.
The second layer of polycrystalline silicon 22 and 23 (pattern of dots) with holes 3 and 14 formed to form the channel, source, and drain of the thin film transistor.
and selectively diffuse P ⁺ . Furthermore, after depositing the third field film 35 and opening the contact holes 15 and 16,
Al--Si layers 24, 25, and 26 are formed. As a result, the N ⁺ diffusion layer 31 is connected to the (+) power supply V _DD in the N channel transistor with the source connected to the (-) power supply V SS, 32 as the drain, and the polycrystalline silicon 20 as the gate and the polycrystalline silicon _layer 22. A P-channel transistor having a source 55, a channel 54, a drain 56, and the polycrystalline silicon 20 as a gate is formed, and a CMOS random access memory can be constructed in which each drain is connected via a diode.

FIG. 5 shows a circuit diagram of the cell pattern shown in FIG. 2. N-channel transistors 40 to 43 are formed in bulk silicon single crystal, and P-channel transistors 44 and 45 are formed as polycrystalline thin film transistors. Diodes 46 and 47 are polycrystalline silicon diodes that occur at the connection point between the P channel and N channel transistors, and by interposing an N ⁺ polycrystalline silicon layer that is polymerized with the P ⁺ polycrystalline silicon layer, these diodes can be , it becomes a diode formed by partially overlapping polycrystalline silicon layers, and has a large leakage current and a large junction area, so it has low resistance and does not interfere with the operation of silicon memory.

In general, it is known that polycrystalline silicon layers have extremely low mobility and poor transistor characteristics compared to single-crystalline silicon, and in particular have a large OFF leakage current. However, as a result of our efforts to improve this characteristic, the inventors discovered the following. As shown in Figure 3, the deposition temperature of polycrystalline silicon was set to 700℃.
When the temperature is below, the mobility is improved, and a characteristic close to 10 was obtained especially near 500°C. In addition, improving OFF leakage depends on the manufacturing method between the gates, which is made by thermally oxidizing polycrystalline silicon, and dry oxidation at high temperatures is the best method. Furthermore, even if the deposition temperature of the polycrystalline silicon layer is high, it is possible to improve mobility and OFF leakage by performing laser annealing.

Figure 4 shows the process of depositing polycrystalline silicon at 500°C, then lightly doping P ions into the channel area by ion implantation, and forming a gate oxide film.
Characteristics of transistors of the same size as those used in memory cells formed at 1100°C.
The properties are sufficient for memory applications.

Furthermore, since the data line is placed above the silicon layer portion forming the channel region of the thin film transistor with an insulating film interposed therebetween, the channel region is influenced by the potential of the data line. When a flip-flop is constructed by cross-connecting the inputs and outputs of two inverters, the electric field of the gate electrode to the channel region and the electric field of the data line to the channel region may be opposite, and the operation of the flip-flop may be affected. Becomes unstable. Therefore, by arranging the data line with an insulating film thicker than the gate insulating film intervening, the electric field due to the gate electrode can always be made larger than the electric field from the data line, and the thin film transistor is able to control the control of the gate electrode. This prevents the operation from becoming unstable.

As described above, by forming a thin film transistor having a source and drain region spaced apart from each other across a channel region in a silicon layer disposed above a substrate, and by disposing a data line above this thin film transistor, , the size of the memory cell can be reduced, and the data lines can be
By placing an insulating film that is thicker than the gate insulating film formed on one surface of the silicon layer that forms the channel region of the thin film transistor above the silicon layer, the thin film transistor is affected by the data line. This has the effect that stable operation can be guaranteed without any problems.

[Brief explanation of drawings]

FIG. 1 is a cell diagram of a CMOSRAM. FIG. 2a is a plan view of a CMOSRAM according to the present invention;
Figure b shows a cross-sectional view. FIG. 3 is a diagram showing the relationship between the mobility of polycrystalline silicon and the deposition temperature, and FIG. 4 is a diagram showing the characteristics of a polycrystalline silicon transistor obtained according to the present invention. FIG. 5 is a circuit diagram of FIG. 2. 10, 11, 12, 13, 14, 15, 16...
...Contact hole, 19, 20, 21, 27...
...First layer polycrystalline silicon, 22, 23... Second layer polycrystalline silicon, 30... Substrate, 31,
32, 33...source/drain, 54...channel, 55...source, 56...drain.

Claims (1)

[Claims] 1. A memory cell formed by cross-connecting the input and output of two inverters configured by connecting a MOS transistor and a thin film transistor in series between power supplies, respectively, is formed on the surface of a substrate and above the substrate, In the random access memory having a data line for transmitting data to and from the memory cell, the MOS transistor has a source and a drain region formed on the surface of the substrate and spaced apart from each other with a channel region in between. The thin film transistor has a source and drain region formed in a silicon layer disposed above the substrate and spaced apart from each other with a channel region in between, and the data line is a silicon layer forming the channel region of the thin film transistor. A random access memory characterized in that an insulating film that is thicker than a gate insulating film formed on one surface of the layer portion is disposed above the silicon layer portion.