JPH0422480Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital data sampling circuit.

[Background Art] With the introduction of digital technology in recent audio equipment, the following devices have been put into practical use.

After sampling the audio signal and converting it to digital data, it is recorded on optical disk or magnetic tape with special signal processing, and then
After reading the digital data recorded from these information recording media and performing the signal processing opposite to the above,
It performs digital-to-analog conversion to restore the original audio signal.

The above digital data is each digital data Dk
Serial data is given as ……D _k D _k-1 D _k-2 ……D ₁ D ₀ …… and constitutes one data in synchronization with the word clock. This data corresponds to the analog value of the original audio signal.

In such audio equipment, for example, when the peak value of an audio signal is to be displayed, this peak value is directly detected from the data.

As shown in FIG. 4, the above data is obtained by sampling the original audio signal at a period T, but since this is not practical due to the relationship with the data processing time, conventionally, data groups have been sampled at the sampling period T.
Sampling is performed at a period NT (N≧2) that is N times larger than
The peak value is detected from the sampled data.

[Problem to be solved by the invention] In the conventional technology, since N is constant, if the period of the original audio signal is less than 2NT, as shown in Figure 4 (dashed line), the sampling theorem allows accurate measurement. Unable to detect peak value.

[Means for solving the problem] In the present invention, the value of N described above is N ₀ +n ₀ (n ₀ =0, 1...) corresponding to the period of the original signal, where N ₀ is the period of the original signal. Determined by the minimum weekly period.

A shift register 1 which is variable as shown in FIG. The latch circuit 2 is provided with a latch circuit 2 that latches in response to a latch enable signal, and the period of the latch enable signal is changed.

The means for changing the period of the latch enable signal includes a binary counter 4 that counts the word clock with preset contents as an initial value, and changes the contents preset in the binary counter 4. , is something.

[Effect] In the above configuration, its operation will be explained.

For the sake of simplicity, the explanation will be made with reference to an embodiment in which the BCD counter 3 and the binary counter 4 are constituted by 4-bit counters.

(1) In the initial state, the content of BCD counter 3 [Q _H Q _G Q _F Q _E ] is [0000], and the content of binary counter 4 [Q _D Q _C Q _B Q _A ]
is [0000].

In this state, the output of binary counter 4 [Q _D ]
Since the AND output X (=Q _D ·Q _C ) of [Q _C ] is [0], the BCD counter 3 maintains the above initial state.

(2) Binary counter 4 counts 16 word clock WCLKs from the initial value [0000], and when the count value reaches the full count [1111], it issues a ripple carry-out signal.
RCO outputs, and at the same time, the AND output X (=Q _D · Q _C ) becomes [1].

The BCD counter 3 counts this AND output X, and the content becomes [0001].

The content [0001] of this BCD counter 3 is preset into the binary counter 4 by (the falling edge of) the ripple carry-out signal RCO.

Meanwhile, the above ripple carry out signal
The AND output of RCO and a signal obtained by inverting the word clock WCLK is input to the latch circuit 2 as the latch enable signal LE.

As a result, among the data sequentially output from the shift register 1, the 16th data is latched by the latch circuit 2 and output.

This is a period 16 times the sampling period T.
This means that it was sampled at 16T.

(3) Binary counter 4 starts counting with the newly preset content [0001] as the initial value, and when 15 word clocks WCLK have been counted, the content of BCD counter 3 becomes [0001] in the same manner as above. ] becomes.

The content [0010] of this BCD counter 3 is 2
It is preset in advance counter 4.

On the other hand, similarly, the latch enable signal
LE is created, and the 15th data among the data sequentially output from the shift register 1 is latched by the latch circuit 2.
Output.

This is a period 15 times the sampling period T.
This means that it was sampled at 16T.

(4) Similarly, when the content [Q _H Q _G Q _F Q _E ] of the BCD counter 3 becomes [0111] as shown in Figure 2, this content [0111] is changed to the binary counter 4.
Preset to .

Binary counter 4 starts counting with this content [0111] as the initial value, and when it counts 9 word clock WCLKs, the content of BCD counter 3 becomes [1000] in the same way, and this content becomes binary. The counter 4 is preset.

On the other hand, similarly, the latch enable signal
LE is created and input to the latch circuit 2 described above.

As a result, of the data sequentially output from the shift register 1, the ninth data is latched by the latch circuit 2 and output.

This is a period 9 times the sampling period T.
This means that it was sampled at 9T.

Thereafter, in the same way, the binary counter 4 starts counting with the newly preset content [1000] as the initial value, and when the word clock WCLK has been counted 8 times, the latch enable signal LE is generated. Then,
Of the data sequentially output from the shift register 1, the eighth data is latched by the latch circuit 2 and output.

This is a period eight times the sampling period T.
This means that it was sampled at 8T.

(5) Then, the content of the BCD counter 3 changes from [1000] to [1001], and accordingly, the content of the binary counter 4 also changes from [1000] to [1001].

The binary counter 4 starts counting with its content [1001] as the initial value, and when it counts 7 word clocks WCLK, the latch enable signal LE is generated.
Of the data sequentially output from the shift register 1, the seventh data is latched by the latch circuit 2 and output.

This is a period that is 7 times the sampling period T.
This means that it was sampled on 7T.

On the other hand, at this point, the content of BCD counter 3 becomes the full count value, so it is reset and (1)
Return to the initial state.

Thereafter, the same operation is repeated.

To summarize, the contents of BCD counter 3 [Q _H Q _G Q _F
Q _E ] changes from the initial state [0000] to [0001] [0010] : [1000] [1001], and the contents of binary counter 4 change accordingly [Q _D Q _C Q _B Q _A ] also changes from [0000] to [0001] [0010] : [1000] [1001].

Therefore, since the binary counter 4 repeats the counting operation using these contents as initial values, the counted number decreases as 16, 15, 14, . . . 8, 7.

This means that the sampling period T 16x, 15x...8x, 7x period, i.e., 16T, 15T, 14T...8T, 7T This means that it was sampled.

FIG. 3 is an operation explanatory diagram showing such a sampling operation.

[Embodiment] FIG. 1 shows the configuration of an embodiment of the sampling circuit of the present invention. In this embodiment, the value of N is 7(N ₀ )+n ₀ (n ₀ =0, 1... ...9) In other words, it is configured to change in nine stages: 16, 15, 14...8, 7.

Figure 2 is the same, signal waveform diagram of each part, Figure 3 is the same,
It is an operation explanatory diagram.

1 is a shift register in which serial data (Fig. 2b) from data input 1a...D _k D _k-1 D _k-2 ...D ₁ D ₀ ... is synchronized with the bit clock (Fig. 2 a). They are entered sequentially.

This serial data is the word clock WCLK.
(Fig. 2c) and constitutes one data. This data corresponds to the analog value of the original signal.

2 latches the output data sequentially output from the shift register 1 in synchronization with the latch enable signal LE (Fig. 2 e), thereby converting the above data into 9
This is a latch circuit that samples and outputs the value of N in stages. That is, the latch enable signal
The period of LE is 16T, 15T...8T, 7T. However, T: sampling period is changed in 9 steps.

This latch enable signal LE is a binary 10 clock that operates based on the word clock WCLK.
Binary (BCD) counter 3 (BCD-binary-coded
(desimal) and binary counter 4.

The binary counter 4 counts the word clock WCLK from the set initial value and outputs a count output [Q _D Q _C Q _B Q _A ].

The output [Q _D ] [Q _C ] of this binary counter 4 is the first
The AND outputs X (=Q _D ·Q _C ) (FIG. 2f) are input to the clock input of the BCD counter 3.

This BCD counter 3 is the first AND output
, and outputs a count output [Q _H Q _G Q _F Q _E ], which is input to inputs A, B, C, and D of the binary counter 4, respectively.

The binary counter 4 outputs a ripple carry-out signal when its count value reaches a full count.
RCO is output, which presets the count output [Q _H Q _G Q _F Q _E ].

The binary counter 4 counts the word clock WCLK using its contents [Q _H Q _G Q _F Q _E ] as an initial value, and when it reaches the full count value, it outputs the count from the BCD counter 3 in the same way as above. is preset, and the same operation is repeated thereafter.

On the other hand, word clock WCLK is inverted by inverter circuit 6 and then input to second AND circuit 7 together with ripple carry-out signal RCO. AND of this second AND circuit 7
The output is input to the latch circuit 2 as the latch enable signal LE.

[Effect of the invention] The present invention has a configuration in which data is sampled at a period NT (N≧2) that is N times the sampling period T of the original signal, and the above N is Since the value is made variable, accurate sampling can be performed even with periodic changes in the original signal, which is effective.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the sampling circuit of the present invention, FIGS. 2 and 3 are signal waveform diagrams and operation explanations of each part, and FIG. 4 is a diagram showing the configuration of a conventional sampling system. FIG. 1...Shift register, 2...Latch circuit, 3
... BCD counter, 4 ... Binary counter, 5,
7...First and second AND circuits, 6...Inverter circuit.

Claims (1)

[Claims for Utility Model Registration] 1. A shift register 1 into which serial data consisting of one piece of data is sequentially input in synchronization with a word clock, and a latch in which data sequentially output from the shift register 1 is synchronized with the word clock. 1. A sampling circuit comprising a latch circuit 2 that latches in response to an enable signal, the sampling circuit comprising: a latch circuit 2 that latches in response to an enable signal, and the period of the latch enable signal is varied. 2. Utility model registration claim 1, comprising a binary counter 4 that counts the word clock using preset contents as an initial value, and the contents preset in the binary counter 4 are changed. Sampling circuit described in section.