JPH0423056A - Ram circuit - Google Patents

Abstract

PURPOSE:To prevent the natural destruction of data and to improve the reliability of a RAM circuit by writing again the data read once into the RAM. CONSTITUTION:When no data is read out by a microinstruction in a normal execution state and an invalid flag 2 is set at logic 1, a write flag 8 functions to input the write flag negative data 104 of a NOT circuit 7 for each clock. Thus the read data 113 on a RAM circuit is stored in a register 12. Under such conditions, a 2nd selection circuit 5 selects the rewrite address data 108 on a counter 1 as the address data 109. Thus the write data 112 is stored in the rewrite address of the counter 1.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a RAM circuit, and more particularly to a RAM circuit from which stored data is read by microinstructions.

BACKGROUND ART Conventionally, in a RAM circuit in which stored data is read by a microinstruction, a parity check or an FCC check is generally performed when reading data to ensure the validity of the data.

This conventional RAM circuit that performs reading using microinstructions checks the validity of data at the time of reading.
Although it is checked by the CC correction circuit, if -U data is written and then only read, data at an address such as 0 may be naturally destroyed if reading is not carried out for a long time. There is a problem that the reliability is low because there is a possibility that a fatal error of 2 or more bits will occur.

OBJECTS OF THE INVENTION An object of the present invention is to provide a RAM circuit which improves reliability by preventing natural destruction of data at addresses where reading is not performed simultaneously for a long time.

Structure of the Invention According to the present invention, in a RAM circuit in which data is read by an instruction, when the read processing by the instruction is not executed, the contents are updated once every two clocks, and the address of the RAM is updated. a counter that generates the above 2
a read control means for reading data from the RAM and performing error correction at one time before the clock; and a write control means for writing the data read by the read control means back into the RAM at V after the two clocks. A RAM circuit is obtained which is characterized in that it includes the following.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

The figure is a block diagram of a RAM circuit according to an embodiment of the present invention.

The RAM circuit of this embodiment includes a counter 1 that serves as the address of the RAM circuit 6 when not read by a microinstruction, an invalid flag 2 that indicates that the microinstruction is invalid, and an address register 3 that stores address data 106 during normal execution. , the first selection circuit 4 selects the external data 110 or the output Ill of the read register] 2 as the write data to the RAM circuit 6, and the output 107 of the address register 3 or the output of the counter 1 as the address data to the RAM circuit 6. 1.08, a RAM circuit 6 that outputs data 113 according to a microinstruction, a negation circuit 7 that outputs the negation logic of the output 103 of the write flag 8, a write instruction I00, and an output 102 of the invalid flag 2. ,
A write signal generation circuit 9 generates a write signal for read data based on the output 104 of the NOT circuit 7, and a read data 11.
3, an AND circuit 11 which receives the write command 100 and the output 104 of the NOT circuit 7, and a read register which stores read data 114.

First, at the time of initial writing to the RAM circuit 6, the invalid flag 2 is set.
is logic O, the first selection circuit 4 selects the write data 110.
is selected and outputted as the second write data, and the second selection circuit 5 selects the data 107 of the address register 3 and outputs it as the address data 109 of the RAM circuit 6.

At this time, under the conditions that the write command +00 is logic 1 and the invalid flag 2 is logic O, the write signal generation circuit 9 sets the write signal 105 to logic 1, so the RAM circuit 6 inputs the address specified by the address register 3. Write data 11
Data of 0 is written.

Writing is completed by changing the address data 106 by 1 from 00 to 4FF (hexadecimal) and writing one word at a time.

Next, when data is being read by a microinstruction during normal execution, the write command 100 is at logic o1 and the invalid flag 2 is at logic O, so the write signal generation circuit 9 outputs logic O as the write signal 105. do.

Since the invalid flag 2 is logic 0, the second selection circuit 5 selects the data 107 of the address register 3 and sets it to address data 1.
Output as 09. Read data 11 of RAM circuit 6
3 is sent to the ECC check correction circuit 1 ( ) and output as read data 114 .

Next, when data is not read by a microinstruction during normal execution, the write instruction 100 becomes logic 0 and the invalid flag 2 becomes logic 1. Since the write flag 8 inputs the write flag negation data 104 of the negation circuit 7 every clock when the invalid flag 2 is logic 1, the data of the write flag 8 is updated as 0-.1→0. Since the counter 1 is updated when the write flag 8 is logic 1, it is updated every two clocks.

When the write flag 8 is logic 0, the RAM circuit 6 performs a read operation, and the write signal generation circuit 9 receives the write command 10.
0, write logic 0 including the invalid flag 2 condition, signal 1
Output as 05. Since counter 1 is not updated, it outputs the initial value 00, and invalid flag 2 is set to logic 1, so the counter 1 outputs the initial value 00.
The selection circuit 5 outputs the data 108 of the counter 1 as address data 109. Due to the invalid flag data 102 of the invalid flag 2 and the write flag negation data 104, the read register set signal +15 output from the AND circuit 11 becomes logic 1, so the read data 113 at address 00 of the RAM circuit 6 is ECC corrected. It passes through the circuit 10 and is stored in the read register 12.

At the next clock, write flag 8 becomes logic 1, and the RAM
Moving on to the rewriting operation to the circuit 6. Invalid flag 2 is logic 1
Therefore, the first selection circuit 4 outputs the rewrite data Ill of the read register 12 as the write data 112. The write signal generation circuit 9 outputs logic 1 as the write signal 105 according to the conditions of the write command 1OO1 invalid flag 2.

At this time, since the invalid flag 2 is logic 1, the second selection circuit 5 selects the rewrite address data of the counter 1! Since 08 (00 in this case) is selected as address data 109, write data 112 is stored at this address. The data of counter 1 is updated with this clock, and the data changes by 1 from 00 to FF, and a rewrite operation is performed for all words. After rewriting to address FF, counter 1 is reset to 00 again and the rewriting operation continues.

As described in detail, the present invention reads and rewrites the RAM circuit sequentially for all addresses when no reading is being performed by microinstructions, so that reading by microinstructions can be carried out for a long time. This has the effect of preventing data from being spontaneously destroyed and improving reliability of data at addresses that may not be transmitted.

[Brief explanation of drawings]

The figure is a block diagram of an embodiment of the present invention. Explanation of symbols of main parts 1...Counter 2...Invalid flag 6...RAM 7...Negation circuit 8...Light flag 9...Write signal generation circuit 10...ECC check circuit 12...Read register

Claims (1)

[Claims] (1) A RAM circuit in which data is read by an instruction, and when the read processing by the instruction is not executed, the contents are updated once every two clocks and the RA
a counter that generates an address of M; read control means that reads data from the RAM and performs error correction in the first half of the two clocks; R.A.
R characterized in that it includes a write control means for writing to M.
AM circuit.