JPH04310136A - Control storage correcting circuit - Google Patents

Abstract

PURPOSE:To prevent the reduction of the processing speed at the time of the occurrence of an error. CONSTITUTION:An information processing mechanism 10 switches an address selector 34 to a check address from a normal control storage address by a wait signal that shows a wait state produced from the synchronization secured with an external input device or at the access to a memory outside the mechanism 10. The contents of a control storage pointed by the check address are taken out by a check register 3, and the ECC check is carried out without disturbing the execution of the mechanism 10. Then the time is secured for the mechanism 10 to write the corrected contents into the control storage with a new wait signal when an error is detected. Thus a control storage correcting circuit can write the corrected contents into the control storage.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control memory modification circuits.

0002

[Background Art] Conventionally, checking and correction of control memory is performed when a control program is executed, and if an error occurs, a wait signal is output to cause the information processing device to wait, correct the error, and transfer the control memory to the control memory. is writing.

0003

[Problems to be Solved by the Invention] In the conventional control memory correction method described above, since the control program is checked and corrected when it is executed, correction and writing processes are performed every time an error occurs, and the program Execution is delayed and processing speed is affected.

Furthermore, if a soft error occurs in two or more bits in one word of a control program due to alpha rays, it becomes impossible to correct it using the currently commonly used 1-bit error correction method using ECC.

[0005]

[Means for Solving the Problems] The circuit of the present invention provides an ECC
In a control memory correction circuit in an information processing mechanism that has a control memory that detects and corrects a 1-bit error using and an address selector that switches between the normal control storage address and the check address using a wait signal indicating a wait state that occurs when the information processing mechanism synchronizes with an external input device or when accessing a memory outside the information processing mechanism. , a check register that holds the contents of the control memory for checking, and an OR gate that logically ORs the error with the wait signal to generate a new wait signal if there is an error in the ECC check of the check register. Then, by the wait signal, the address selector is switched from the normal control memory address to the check address, the contents of the control memory indicated by the check address are loaded into the check register, and the ECC check is performed without interfering with the execution of the information processing mechanism. The present invention is characterized in that when an error occurs, a new wait signal is used to ensure time for the information processing mechanism to write the modified contents of the control memory to the control memory, and to write the modified contents of the control memory to the control memory. .

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. 10 in the figure is an information processing mechanism using the present invention. The contents of the information processing mechanism 10 are stored in the control memory 4 of the processing execution unit 20.
It is broadly divided into 0 and 0.

The control memory 40 outputs the content (hereinafter referred to as CS data) specified by the control memory address (hereinafter referred to as CS address) 41 output from the processing execution unit 20 (
It is output to the CS data bus (hereinafter referred to as the CS data bus) 43. The CS data bus 43 is bidirectional, and when the write instruction signal 42 from the processing execution unit 20 is "1", the value on the CS data bus 43 is written to the address indicated by the CS address 41.

The processing execution section 20 includes the following components. Three of the CS address register 21, the check address register 31, and the history register 33 that holds a value minus 1 of the value of the check address register 31 are given to the control memory 40 as a CS address 41 through the address switching selector 34.

Switching of the selector 34 is determined by a combination of a new wait signal 27 and an error signal 38 from an ECC checker and correction section (hereinafter referred to as check circuit) 37. Table 1 shows the combination conditions.

[0011]

The check circuit 37 is activated by the wait signal 26. The increment circuit 32 of the check address register 31, the history register 33, and the check address register 31 receives instructions from the check circuit 37.
is controlled.

Reference numeral 23 in the figure indicates a wait factor generated within the processing execution section 20, and a wait signal 26 is generated by the wait signal generation section 22. The new wait signal 27 is obtained by ORing the wait signal 26 and the error signal 38 by the RO gate 35.
and generated. When a check is performed in the CS register register 24, which is normally executed and CS data is stored, it is stored in the check register 36.

In the figure, 50 is a system bus to which the information processing mechanism 10 is connected, and 60 is a bus device connected to the system bus 50.

The information processing mechanism 10 operates as follows when the new wait signal 26 does not become "1".

The value of the CS address register 21 is output as the CS address 41. The corresponding CS data is CS
The CS data is output to the bus 43 and stored in the CS register 24, and the decode circuit 25 decodes and executes the CS data. As a result, the next CS address to be executed is determined and the value of the CS address register 21 is updated. By repeating this, the processing execution unit 10 advances the processing. In this state, this control memory modification is not executed.

Assume now that the processing execution unit 10 issues a read request to the memory device 60 and one of the wait factors 23 becomes valid. The wait signal generation circuit 22 makes the wait signal 26 valid, and thereby the check circuit 37
is started.

The address selector 34 selects the CS address 41
Switch the output of check address 31 to the output of CS
CS data corresponding to the output of the check address 31 is output to the data bus 43 and stored in the check register 36.

The contents of the check address register 31 and the history register 32 are updated at the same timing. The output of the check register 36 is performed by a check circuit 37. This checking operation is repeated while the wait signal 26 is valid.

When the wait signal is no longer valid, the value of the CS address 21 is output as the output of the address register 34, returning to the normal state and processing is executed.

When the check circuit 37 detects a 1-bit error, the error signal 38 becomes valid and the output of the CS address selector 34 is switched to the value of the history register 33. The history register 33 is used because the value of the check register 31 has already been updated to the value of the CS address where the error was detected +1.

The check circuit 37 outputs the modified CS data onto the CS bus, enables the write instruction signal 42, and writes the modified CS data into the control memory 40. The reason why the error signal 38 is ORed with the wait signal 26 to generate the new wait 27 is to prevent the wait signal 26 from switching the CS address 41 during writing to the control memory 40.

[0023]

[Effects of the Invention] As explained above, since the processing execution unit performs checking and correction while in a wait state, there is no reduction in processing speed due to correction and writing processing every time an error occurs, and This has the effect of reducing the probability that soft errors caused by alpha rays will occur in two or more bits in one word of the control program, resulting in an uncorrectable state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

10 Information processing mechanism 20 Process execution unit 21 CS address register 22 Wait signal generation circuit 23 Wait signal cause 24 CS data register 25 Decode circuit 26 Wait signal 27 New wait signal 31 Check address register 32 Increment circuit 33 History register 34 CS address selector 35 OR gate 36 Check register 37 Check circuit 38 Error signal 40 Control memory 41 SC address 42 Write instruction signal 43 SC data bus 50 System bus 60 Memory device

Claims (1)

[Claims] Claim 1. In a control memory correction circuit in an information processing mechanism having a control memory that detects and corrects one-bit errors using ECC, a check address dedicated to checking the contents of the control memory and a check address for checking the contents of the control memory are provided. An increment circuit that adds 1 and a wait signal that indicates a wait state that occurs when the information processing mechanism synchronizes with an external input device or when accessing a memory external to the information processing mechanism are used to convert the normal control memory address and the above-mentioned check. An address selector that switches addresses, a check register that holds the contents of control memory for checking, and if there is an error in the ECC check of the check register, a new wait signal is generated by ORing the error with the wait signal. The wait signal causes the address selector to switch from a normal control memory address to a check address, and the contents of the control memory indicated by the check address are loaded into the check register, and the information processing mechanism is executed. The ECC check is performed without interfering with the process, and if there is an error, a new wait signal is used to secure time for the information processing mechanism to write the modified contents of the control memory to the control memory. A control memory correction circuit characterized by writing.