JPH04233739A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To improve characteristics by steepening the gradient of carrier concentration in the direction of depth of an active layer without increasing internal resistance. CONSTITUTION:The characteristics of the title transistor is that it is equipped with an active layer 2 consisting of a semiconductor of one conductivity type, a gate electrode 7 to be provided on one surface of the active layer 2 and a Schottky junction with the layer 2 will be formed, a source electrode 8 and a drain electrode 9 where an ohmic connection is formed with the active layer 2 provided leaving the prescribed distance from the gate electrode 7, and an opposite conductivity type region 12 having the other conductivity type consisting of the above-mentioned semiconductor which is the part of the other surface of the active layer 2 and provided on the region opposing to the gate electrode 7.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to field effect transistors, and more particularly to field effect transistors (hereinafter also referred to as FETs) which have a steep carrier concentration gradient in the region immediately below the gate electrode in the active layer, resulting in excellent characteristics. It is.

0002

BACKGROUND OF THE INVENTION Generally, the characteristics of an FET depend on the carrier concentration distribution in the depth direction of the active layer, and the steeper the concentration gradient, the more uniform the mutual conductance gm can be obtained, and the characteristics can be improved. Are known.

One of the methods for forming the active layer is ion implantation, but when the active layer is formed using this method, the carrier concentration gradient in the depth direction becomes gentle in the low concentration region deep in the ion implanted layer. It is difficult to hope for improved characteristics.

On the other hand, self-alignment methods have been widely used in recent years to reduce the source resistance of FETs and to improve characteristics by keeping the gate-source and gate-drain distances constant.

FIG. 3 shows a structure in which an n-type active layer 2 is formed on a p-type buffer layer 13 using such a self-alignment method, and the carrier concentration gradient in the depth direction of the active layer 2 is made steep. A conventional GaAs MESFET is shown. In the figure, 1 is a semi-insulating GaAs substrate, and an n-type active layer 2 and a p-type buffer layer 13 are formed over the entire surface of the substrate 1 by ion implantation or epitaxial growth. 3 is an n+ source region, 4 is an n+ drain region, 5 is a silicon nitride film, 6 is a silicon oxide film, and 7 is a gate electrode, and the gate electrode 7 forms a Schottky junction with the active layer 2. 8 is a source electrode, 9 is a drain electrode, the source electrode 8 is ohmically connected to the n+ source region 3, and the drain electrode 9 is connected to the n+ drain region 4.
It is ohmic connected to.

[0006]

[Problems to be Solved by the Invention] Conventionally, the p-type buffer layer was formed over the entire surface of the substrate, so when the gate-drain distance was increased in order to improve the breakdown voltage, the internal resistance (source・There was a problem in that the resistance between the drains increased and the gain decreased.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a field effect transistor that can steepen the carrier concentration gradient in the depth direction of the active layer without increasing the internal resistance and improve the characteristics. .

[0008]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention includes an active layer made of a semiconductor having one conductivity type, and an active layer provided on one surface of the active layer and having a Schottky contact with the active layer. A gate electrode forming a junction, a source electrode and a drain electrode provided at a predetermined distance from the gate electrode and forming an ohmic contact with the active layer, and a portion on the other surface of the active layer and the gate electrode. and an opposite conductivity type region formed of the semiconductor having the other conductivity type and provided in an opposing region.

The opposite conductivity type region is preferably formed by ion implantation.

The active layer portion where the source electrode and the drain electrode are ohmically connected is formed to have a higher carrier concentration than other active layer portions.

[0011]

[Function] Only in the active layer region facing the gate electrode is an opposite conductivity type region that is different from the conductivity type of the active layer, so the carrier concentration gradient in the depth direction of the active layer directly under the gate electrode is It becomes steep. Furthermore, the active layer between the gate and the source and between the gate and the drain has a higher thickness and carrier concentration than the portion directly under the gate electrode, so that the internal resistance is not deteriorated. Therefore, improved characteristics such as improved gm and gain especially near the pinch-off voltage can be obtained.

0012

Embodiments Hereinafter, embodiments of the present invention will be explained based on FIGS. 1 and 2.

This embodiment is applied to a GaAs MESFET.

In FIGS. 1 and 2, members and parts that are the same or equivalent to those in FIG. 3 are designated by the same reference numerals.

First, using FIG. 1, GaAsMESFE
The structure and operation of T will be explained.

In this embodiment, on the other surface (lower surface) of the n-type active layer 2 and in the region facing the gate electrode 7,
A p-type opposite conductivity type region 12 is formed by being buried by ion implantation.

Since the GaAs MESFET of this embodiment is constructed as described above, the carrier concentration gradient in the depth direction of the active layer 2 is steep only in the pinch-off portion directly below the gate electrode 7. In addition, the parts of the active layer 2 between the gate electrode 7 and the source electrode 8 and between the gate electrode 7 and the drain electrode 9 have a higher thickness and carrier concentration than the part directly below the gate electrode 7, and have an internal resistance ( The source-drain resistance (resistance between source and drain) does not deteriorate. Therefore, improved characteristics such as improved gm and gain especially near the pinch-off voltage can be obtained.

Next, an example of the manufacturing method will be explained using FIG. 2.

[0019] In the following explanation, (a) to (d)
Each item symbol corresponds to each of (a) to (d) in FIG.

(a) S on the main surface of the semi-insulating GaAs substrate 1
An n-type active layer 2 is formed by ion-implanting i to a depth of 0.3 μm and a doping amount of about 4×10 12 cm −2 . On the substrate 1 on which the active layer 2 has been formed, a silicon nitride film 5 is formed as a first insulating film by a plasma CVD method, and a silicon oxide film 6 is formed as a second insulating film thereon by the same plasma CVD method. do. Subsequently, a gate electrode opening, a source region opening, and a drain region opening are formed in the silicon oxide film 6 by dry etching using the photoresist in which the opening has been formed as a mask.

(b) A photoresist 10 is formed to cover the gate electrode opening. Using this photoresist 10 and silicon oxide film 6 as a mask, Si was deposited to a depth of 0.8 μm.
Ions are implanted to a doping amount of approximately 5×10 13 cm −2 to form an n+ source region 3 and an n+ drain region 4.

(c) After removing the photoresist 10 in the gate electrode opening, a photoresist 11 is formed to cover the source region opening and the drain region opening. Using this photoresist 11 and silicon oxide film 6 as a mask, B
The n-type active layer 2 is formed by ion implantation and annealing.
A p-type opposite conductivity type region 12 is formed so as to be buried in the other surface (lower surface) of the gate electrode and in the region facing the gate electrode. The energy during Be ion implantation is such that the projected range of Be ions is larger than the projected range during Si ion implantation for forming the n-type active layer 2, and the peak carrier concentration is such that the projected range of Be ions is higher than that of Si ions. The doping amount is about 1×10 12 cm −2 which does not exceed the peak carrier concentration of .

(d) After selectively removing the silicon nitride film 5 at the gate electrode opening, the source region opening, and the drain region opening, a T-shaped gate electrode 7 and an n+ source are formed to form a Schottky junction with the active layer 2. A source electrode 8 making an ohmic contact with the region 3 and a drain electrode 9 making an ohmic contact with the n+ drain region 4 are formed, respectively.

According to the above manufacturing method, since both the n-type active layer 2 and the p-type opposite conductivity type region 12 are formed by ion implantation, the carrier concentration and depth can be easily controlled, and the active Reverse conductivity type region 1 is accurately placed on the bottom surface of tank 2.
2 can be formed. Further, the active layer structure directly under the gate electrode has an LDD structure, and the gate breakdown voltage can be improved.

Since the self-alignment method is used, the gate-source distance and the source-drain distance can be set independently, making it easy to obtain desired breakdown voltage characteristics. Since the gate electrode can be formed into a T-shape, the internal resistance of the electrode can be lowered.

[0026]

[Effects of the Invention] As explained above, according to the present invention, an opposite conductivity type region opposite to that of the active layer is provided only in the region on the other side of the active layer and facing the gate electrode. , the carrier concentration gradient in the depth direction of the active layer can be made steeper without increasing the internal resistance, and the characteristics can be improved.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view showing an embodiment of a field effect transistor according to the present invention.

FIG. 2 is a process diagram showing an example of a method for manufacturing the field effect transistor shown in FIG. 1;

FIG. 3 is a longitudinal cross-sectional view showing a conventional field effect transistor.

[Explanation of symbols]

1 Semi-insulating GaAs substrate 2 N-type active layer 7 Gate electrode 8 Source electrode 9 Drain electrode 12. Opposite conductivity type region

Claims (1)

[Claims] 1. An active layer made of a semiconductor having one conductivity type, a gate electrode provided on one surface of the active layer and forming a Schottky junction with the active layer, and a predetermined distance from the gate electrode, respectively. a source electrode and a drain electrode provided at a distance from each other to form an ohmic contact with the active layer; and a semiconductor having the other conductivity type provided on the other surface of the active layer and in a region facing the gate electrode. 1. A field effect transistor comprising a region of opposite conductivity type.