JPH064406A - Data processor having cache memory - Google Patents

Abstract

(57) [Abstract] [Purpose] An external secondary storage device 5 and an external primary storage device 4 used as a cache memory without interruption of data processing or calculation processing in the central processing unit 2 in the microprocessor 1. (EN) Provided is a data processing device capable of exchanging data between the two and easily connecting an external primary storage device 4 used as a cache memory to the microprocessor 1. [Configuration] On a chip 10 in which a microprocessor 1 is configured, a function of controlling an external primary storage device 4 as a cache memory and exchanging data of an external secondary storage device 5 with data of an external primary storage device 4 is provided. It has an external primary storage control circuit 3 and an external primary storage device register 6 for mapping the external primary storage device 4 used as a cache memory to the external secondary storage device 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device,
More specifically, the present invention relates to a data processing device having a cache memory in which a cache control circuit is connected to a central processing unit and a high speed memory access means can be easily constructed.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional system configuration of a data processing device having a cache memory.

In FIG. 3, reference numeral 1 denotes a microprocessor constructed on one chip, and has a central processing unit 2 built therein. An external primary storage control circuit 3, an external primary storage device 4, and an external secondary storage device 5 are connected to the outside of the microprocessor 1. The external primary storage control circuit 3 controls the use of the external primary storage device 4 as a cache memory.

Although the conventional data processing device having a cache memory is constructed as described above, for example, the same data as the data of the external secondary storage device 5 is held in the external primary storage device 4 used as a cache memory. If so, the operation is as follows.

In this case, the microprocessor 1 completes the external storage access by accessing the external primary storage device 4 used as a cache memory without accessing the external secondary storage device 5.

When the data in the external secondary storage device 5 is not held in the external primary storage device 4 used as a cache memory, the operation is as follows.

When the microprocessor 1 accesses the external primary storage device 4, the external primary storage control circuit 3 confirms that the data to be accessed is not held in the external primary storage device 4 used as a cache memory. Notify the processor 1. In this case, the microprocessor 1 reads the access gymnastics data from the external secondary storage device 5, copies it once to the external primary storage device 4 used as a cache memory, and then accesses the external primary storage device 4 to access it. Read the target data.

[0008]

Since the conventional semiconductor device having the conventional cache memory is configured as described above, the data accessed by the central processing unit in the microprocessor is used as the cache memory. If the data is not held in the external primary storage device, it is necessary to temporarily read the data to be accessed from the external secondary storage device and write it in the external primary storage device used as a cache memory for replacement. There is a problem that the central processing unit of the microprocessor cannot perform data processing or calculation processing during the period of exchanging data between the two storage devices, resulting in a long processing time.

There is also a problem that it is not easy to add an external primary storage device used as a cache memory, and it is necessary to drastically change the system.

The present invention has been made in view of the above circumstances, and is used as an external secondary storage device and a cache memory without interrupting data processing or calculation processing in a central processing unit in a microprocessor. A data processing device having a cache memory capable of exchanging data with an external primary storage device and capable of easily connecting an external primary storage device used as a cache memory to a microprocessor. For the purpose of providing.

[0011]

A data processing device having a cache memory according to the present invention controls an external primary storage device used as a cache memory as a cache memory on a chip in which a microprocessor is formed. An external primary storage control circuit having a function of exchanging data in the external secondary storage device with data in the external primary storage device, and an external primary storage device for mapping the external primary storage device used as a cache memory to the external secondary storage device. And a memory device register.

Further, in the data processing device having the cache memory of the present invention, the microprocessor is provided with the connector capable of directly connecting the external primary storage device.

[0013]

In the data processing device having the cache memory according to the present invention, when the microprocessor accesses the external primary storage device used as the cache memory, the data to be accessed is not held in the external primary storage device. The external primary storage control circuit refers to the external primary storage device register to exchange the data of the external secondary storage device with the data of the external primary storage device without interrupting the calculation operation in the central processing unit. You can

Further, in the data processing device having the cache memory according to the present invention, it becomes possible to directly connect the external primary storage device used as the cache memory to the microprocessor.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof. FIG. 1 is a block diagram showing a system configuration of a data processing device having a cache memory according to the present invention, and FIG. 2 is a schematic diagram showing an appearance of a data processing device having a cache memory of the present invention.

In FIGS. 1 and 2, reference numeral 1 indicates a microprocessor constructed on one chip, and the chip on which the microprocessor 1 is constructed.
A central processing unit 2 and an external primary storage control circuit 3 are built in above 10. An external primary storage device 4 and an external secondary storage device 5 used as cache memories are connected to the outside of the microprocessor 1.

Chips 10 and 50 of the microprocessor 1 and the external secondary storage device 5 are mounted on a substrate 11, and the chips 10 and 50 are connected by a printed wiring (not shown). Further, a connector 7 is provided on the chip 10 in which the microprocessor 1 is configured. By connecting pins of the external primary storage device 4 to the connector 7 of this chip 10, the chip 40 of the external primary storage device 4 is Directly attached.

Incidentally, the external primary storage control circuit 3 controls the use of the external primary storage device 4 as a cache memory. Although the external primary storage control circuit 3 is conventionally connected to the outside of the chip 10 in which the microprocessor 1 is configured, the external primary storage control circuit 3 is built in the microprocessor 1 in the data processing device of the present invention. . Further, the external primary storage control circuit 3 is further provided with an external primary storage control circuit register 6.

Next, the operation of the data processing device having the cache memory of the present invention will be described. First, the operation when the same data as the data in the external secondary storage device 5 is held in the external primary storage device 4 used as a cache memory is as follows.

In this case, the microprocessor 1 completes the external storage access only by accessing the external primary storage device 4 used as a cache memory without accessing the external secondary storage device 5.

The operation when the data in the external secondary storage device 5 is not held in the external primary storage device 4 used as a cache memory is as follows.

When the microprocessor 1 accesses the external primary storage device 4, the external primary storage control circuit 3 confirms that the data to be accessed is not held in the external primary storage device 4 used as a cache memory. Notify the processor 1. In this case, the external primary storage control circuit 3 refers to the external primary storage device register 6 to read the access countermeasure data from the external secondary storage device 5 and copy it to the primary storage device 4. Thereafter, the external primary storage control circuit 3 permits the microprocessor 1 to access the data.

In this way, when the data access permission is given from the external primary storage control circuit 3, the microprocessor 1 accesses the external primary storage device 4 used as a cache memory to obtain necessary data from the cache memory. Read from the external primary storage device 4 used as.

[0024]

As described above in detail, according to the data processing device having the cache memory of the present invention, the central processing unit, the external primary storage control circuit, and the central processing unit are provided on the chip in which the microprocessor is constructed. Since the external primary storage device register that controls the use of this external primary storage device as a cache memory is built-in, it becomes possible to easily and inexpensively configure a high-speed microprocessor system with a cache memory. Further, it becomes possible to exchange the data in the external secondary storage device with the data in the external primary storage device without interrupting the calculation processing by the central processing unit in the microprocessor.

Further, since the external primary storage device can be directly connected to the chip in which the microprocessor is configured, the terminal capacity of the external primary storage device is reduced, and high-speed access is possible even with a slow and inexpensive memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of a data processing device having a cache memory according to the present invention.

FIG. 2 is a schematic diagram showing an appearance of a data processing device having a cache memory of the present invention.

FIG. 3 is a block diagram showing a conventional system configuration of a data processing device having a cache memory.

[Explanation of symbols]

 1 Microprocessor 2 Central Processing Unit 3 External Primary Storage Control Circuit 4 External Primary Storage 5 External Secondary Storage 6 External Primary Storage Register 7 Connector

Claims (2)

[Claims] 1. A central processing unit, an external primary storage device connected to the central processing unit, an external secondary storage device connected to the central processing unit, and a cache memory for the external primary storage device. In the data processing device having an external primary storage control circuit for controlling as an external primary storage control circuit, the external primary storage control circuit is a register for mapping the external primary storage device to an external secondary storage device as a cache memory, and an access by the central processing unit. When the target data is not held in the external primary storage device, a means for exchanging the data between the external secondary storage device and the external primary storage device by referring to the register, and the central operation A data storage device having a cache memory, which is configured on the same semiconductor chip as the processing device. Processing apparatus. 2. The data processing device having a cache memory according to claim 1, wherein the microprocessor includes a connector to which an external primary storage device can be directly connected.