JPH04237352A - Fault processing system for memory device - Google Patents

Abstract

PURPOSE:To avoid the generation of a 2-bit fault by providing this fault processing system with an idle time monitoring circuit for monitoring a memory idle time and a fault checking address for checking a fault in a storage part. CONSTITUTION:The fault processing system is constituted to induce the idle time monitoring circuit 6 for monitoring a memory idle time and the fault checking address 5 for checking the fault of the storage part 1. The storage part 1 stores writing data and an address system circuit 3 forms an address to be read out. The circuit 6 monitors a memory idle time and the address 5 checks the fault of the storage part 1 by using the memory idle time. Thereby, addresses from the 0 order address up to the final address are checked in the idle time.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault handling method for memory devices.

0002

2. Description of the Related Art A conventional failure handling method for a memory device will be described with reference to the drawings. FIG. 2 is a block diagram showing a conventional example. The fault handling method for the memory device shown in FIG. 2 detects faults in the read register 2.

0003

SUMMARY OF THE INVENTION The above-described conventional fault handling methods for memory devices have the disadvantage that faults are discovered only when the memory is used. The cache method that reduces memory accesses has the disadvantage that the larger the cache capacity, the fewer memory accesses are required, making it difficult to detect memory failures early.

0004

[Means for Solving the Problems] A fault handling method for a memory device according to the present invention includes a free time monitoring circuit that monitors memory free time, and a fault check address that uses the memory free time to check for faults in a storage section. It consists of:

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The fault handling method for a memory device shown in FIG. 1 includes a free time monitoring circuit 6 that monitors memory free time, and a fault check address 5 that uses the memory free time to check for faults in the storage unit 1. be done. The storage unit 1 is
It holds write data, and the address system circuit 3 generates an address to be read.

[0007] By doing this, it is possible to check addresses from address 0 to the final address in idle time.

[0008]

[Effects of the Invention] The memory device fault handling method of the present invention is as follows:
Since memory faults can be checked before use, it is possible to avoid occurrence of 2-bit faults.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

1. Storage section 2 Read register 3 Address system circuit 4 Timing circuit 5 Fault check address 6 Idle time monitoring circuit

Claims (1)

[Claims] 1. A fault handling method for a memory device, comprising: a free time monitoring circuit that monitors memory free time; and a fault check address that uses the memory free time to check for faults in a storage unit.