JPH04238103A - Head disconnection detecting circuit - Google Patents

Abstract

PURPOSE:To surely detect a head disconnection regardless of the high and low levels of the frequencies of write data. CONSTITUTION:An output section having output transistors Q12 to Q15 which are turned on and off by the base-emitter voltages of transistors Q5, Q6 for supplying head currents according to the on and off of a pair of switching transistors Q1 and Q3, Q2 and Q4 and output terminals 12a, 12b to obtain detection outputs from the collectors of the output TRs Q12 to Q15 are provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a head disconnection detection circuit. Specifically, in recording and reproducing circuits that perform recording and reproduction on magnetic recording media such as electronic equipment and information equipment,
In particular, thin film heads (TFH)
ad) relates to a circuit for detecting wire breakage.

0002

2. Description of the Related Art FIG. 4 shows a block diagram of a general recording/reproducing circuit. In the figure, during recording, write data that has entered between terminals 1a and 1b is converted into a signal at a level necessary for recording by a write driver 2, and is supplied to a thin film head (hereinafter referred to as head) 3 for predetermined recording. recorded on the medium. On the other hand, during reproduction, the signal reproduced by the head 3 is amplified by the read amplifier 4 and output as read data between terminals 5a and 5b. During recording and playback as described above, the head short detection circuit 6 monitors whether or not the head 3 is disconnected, and if a disconnection is detected, an alarm signal is output from the terminal 7, and the head short detection circuit 8 outputs an alarm signal. The presence or absence of short circuits between the three head terminals is monitored.
If a short circuit is detected, an alarm signal is output from terminal 9. FIG. 5 shows a configuration diagram of an example of a conventional circuit, and FIG. 6 shows an operating waveform diagram. In FIG. 5, the same parts as in FIG. 4 are given the same numbers. In FIG. 5, the switching transistor Q
1, Q3, and switching transistor Q2
, Q4, and head current supply transistor Q5,
Q6 is repeatedly turned on and off depending on the polarity of the write data (FIG. 6(A)) that has entered between terminals 1a and 1b. That is, for example, when terminal 1a is H, transistors Q1 and Q
3 is on, transistor Q6 is on, terminal 1b is high
At this time, transistors Q2 and Q4 are turned on, and transistor Q5 is turned on, so that head currents I3 and -I3 (FIG. 6(B)) flow through the head 3 to perform recording. In this case, in order to suppress the overshoot of head currents I3, -I3, damping resistors Rd1,
Rd2 is used, and its use has a damping effect during reproduction, and also serves as a bias supply to the read amplifier 4.

[0003] Here, the inductance of the head 3 is Lh.
, the direct current resistance of the head 3 is Rh, the voltage between the base and emitter of the transistor is VBE, and the current amplification factor of the transistor is β, then V1 = VCC1 − (R1 I3 / β) − VBEV
2 =V1 -I3 Rh V3 =V2 -Lh (di /dt)V4 =VC
C1 −R1 I1 −VBEV5 =VCC2 −R
L1I4, and the head terminal voltages ■ and {circle around (2)}, that is, the input voltage of the head disconnection detection circuit 6, are as shown in FIG. 6(C). In addition,
In the above formula, Lh (di/dt) is the head current I3
, -I3 is the voltage generated when switching directions. Further, in FIG. 6(C), the reference voltage ■ in the head disconnection detection circuit 6 is {R4 /(R3 +R4)}VCC1. When there is no disconnection in the head 3, the head terminal voltages ■ and ■ are equal to the voltages V1 and V3 as shown in Figure 6(C).
, and never exceeds the reference voltage ■. However, when a disconnection occurs in the head 3, the head current I3 stops flowing, and as a result, the head terminal voltages ■ and ■ reach the voltages VCC1 and V4 as shown in FIG. 6(C).
Exceeds the reference voltage ■. When the head terminal voltages ■, ■ exceed the reference voltage ■, the transistor Q7 or Q8 is turned on, and the detected output voltage ■ from the terminal 7 (FIG. 6(D)) becomes L, confirming that the head is disconnected. This head disconnection detection circuit 6 operates only during recording.

0004

[Problem to be solved by the invention] By the way, Fig. 6(C)
In the waveform diagram, the head terminal voltage is
. Therefore, when the frequency of the write data is low, if a head disconnection occurs, there is no particular problem because the head terminal voltages (2) and (2) exceed the reference voltage (2) as shown in FIG. 7(A). However, if the frequency of the write data is high and a head disconnection occurs, the head terminal voltages ■, ■ will not exceed the reference voltage ■, as shown in Figure 7 (B), and therefore the detected output voltage ■ will not become L. , head disconnection cannot be detected.

That is, in the conventional example, head disconnection is detected by comparing the head terminal voltages (2) and (2), which vary in a curved manner due to parasitic capacitance and charging time constant, with the reference voltage (2). In the case of frequency, there was a problem that head disconnection could not be detected reliably.

SUMMARY OF THE INVENTION An object of the present invention is to provide a head disconnection detection circuit that can reliably detect head disconnection regardless of the frequency of write data.

[0007]

[Means for Solving the Problems] The present invention turns on and off a switching transistor that is turned on and off by write data, and turns on and off by a base-emitter voltage of a head current supply transistor. The configuration includes an output section having an output transistor and an output terminal that obtains a detection output from the collector of the output transistor.

[0008]

[Operation] In FIG. 1, if the head 3 is not disconnected, one of the switching transistors (Q1, Q3
) is on, transistor Q10 is also on, and ■<■
As a result, the head current supply transistor Q5 turns off.
Transistor Q6 turns on and output transistor Q
13 is on, transistor Q12 is off, and terminal 1
2a becomes H, and terminal 12b becomes L. Transistor Q2
, Q4 are on, transistor Q11 is also on,
■<■, the transistor Q6 is turned off, the transistor Q5 is turned on, the transistor Q15 is turned on, the transistor Q14 is turned off, and the terminal 12a becomes H and the terminal 12b becomes L.

On the other hand, when the head is disconnected, when transistors Q1 and Q3 are on, transistor Q1
Since 0 is also on and no head current flows, transistor Q
The emitter of 5 is attracted to the transistor Q1 and the transistor Q5 is turned on, and since ■>■, the transistor Q12 is turned on and the transistor Q13 is turned off, so that the terminal 12a becomes L and the terminal 12b becomes H. When transistors Q2 and Q4 are on, transistor Q11 is also on and no head current flows, so transistor Q6
The emitter of is attracted to the transistor Q2, and the transistor Q6 is turned on, and since ■>■, the transistor Q14 is turned on, the transistor Q15 is turned off, and the terminal 12a becomes L and the terminal 12b becomes H.

The present invention provides a voltage between the base and emitter of the head current supplying transistors Q5 and Q6 (which varies depending on whether or not there is a disconnection in the head 3) and transistors Q10 and Q6.
Transistors Q12 and Q1 depending on whether Q11 is on or off
3, or the configuration is simply switching transistors Q14 and Q15, so detection can be performed regardless of the individual magnitude of the head terminal voltage. Therefore, regardless of the high or low frequency of the write data, disconnection of the head 3 can be detected. Presence can be detected reliably.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an operational waveform diagram. In FIG. 1, the same components as in FIG. 5 are given the same numbers. In FIG. 1, reference numeral 10 denotes a head disconnection detection circuit, which constitutes a main part of the present invention and is composed of transistors Q10 to Q15 and a constant current source 11. Transistor Q1
The base of the transistor Q11 is connected to the input terminal 1a, the base of the transistor Q11 is connected to the input terminal 1b, and their emitters are connected in common to the constant current source 11. Also, the base of transistor Q12 is connected to the base of transistor Q5, and the base of transistor Q13 is connected to the base of transistor Q5.
, and these emitters are commonly connected to the collector of transistor Q10. Further, the base of transistor Q14 is connected to the base of transistor Q6, the base of transistor Q15 is connected to the emitter of transistor Q6, and these emitters are connected in common to the collector of transistor Q11. 12a and 12b are detection output terminals, which are connected to the collectors of transistors Q12 and Q14 and the collectors of transistors Q13 and Q15, respectively.

[0012] First, the case where the head 3 is not disconnected will be described. When terminal 1a is H (Fig. 2(A)), transistors Q1, Q3, Q10, and Q6 are turned on, and the head current becomes -I3 (Fig. 2(B)), and ■<■ (Fig. 2(C)). Therefore, transistor Q5
is off, transistor Q6 is turned on, transistor Q13 is turned on, transistor Q12 is turned off, terminal 12a becomes H, and terminal 12b becomes L (FIG. 2(D)). On the other hand, when terminal 1b is H, transistors Q2 and Q4
, Q11, and Q5 are turned on, and the head current becomes I3.
Since ■<■, transistor Q6 turns off, transistor Q15 turns on, and transistor Q14 turns off.
is turned off, and as above, terminal 12a is set to H, and terminal 12a is set to H.
b becomes L.

In this case, in FIGS. 2(C) and (D),
V1 = VCC1 - (R1 I3 /β) - VBEV
2 =V1 -I3 Rh V3 =V2 -Lh (di /dt)V6 =VC
C1 - R1 I1 V7 = V4 - VBE V5 = VCC2 - RL1I4. Next, a case where the head 3 is disconnected will be described. When terminal 1a is at H level (Fig. 2(A)), transistors Q1, Q3, and Q10 are turned on and no head current flows (Fig. 2(B)), so the emitter of transistor Q5 is drawn by transistor Q1 and is connected to transistor Q5.
is turned on and ■>■ (FIG. 2(C)), so the transistor Q12 is turned on and the transistor Q13 is turned off, and the terminal 12a becomes L and the terminal 12b becomes H (FIG. 2(D)). On the other hand, when the terminal 1b is H, the transistors Q2,
Since Q4 and Q11 are turned on and no head current flows, the emitter of transistor Q6 is connected to transistor Q2.
, transistor Q6 turns on, and since ■>■, transistor Q14 turns on and transistor Q1
5 is turned off, and as above, terminal 12a is set to L and terminal 1 is turned off.
2b becomes H. Head disconnection can be confirmed by the L terminal 12a and the H terminal 12b.

Note that since transistors Q10 and Q11 operate in the same way as transistors Q3 and Q4, transistors Q10 and Q11 are replaced by transistors Q3 and Q4.
It is also possible to substitute it with transistor Q3.
, Q4, when transistors Q12, Q13 and transistors Q14, Q15 are connected to the collectors of transistor Q
Since this will impede the high-speed operation of Q3 and Q4, a configuration as shown in FIG. 1 is used.

The present invention does not compare the head terminal voltages (2) and (2) with the reference voltage (2) as in the conventional example, but compares the base-emitter voltage VBE of the head current supply transistors Q5, Q6 (the disconnection of the head 3). (depending on presence)
and transistors Q12, Q13, or transistor Q14 depending on whether transistors Q10, Q11 are on or off.
, Q15 is simply switched, so
Detection can be performed independently of the individual magnitudes of the head terminal voltages (1) and (2), and therefore, the presence or absence of a disconnection in the head 3 can be reliably detected regardless of the frequency of the write data.

FIG. 3 shows a circuit diagram of another embodiment of the present invention, in which the same components as in FIG. 1 are given the same numbers. The circuit shown in FIG. 3 is a head disconnection detection circuit 10', which corresponds to the head disconnection detection circuit 10 shown in FIG. Figure 3
Inside, 151 and 152 are delay circuits, and terminals 1a and 1b
The voltages ■, ■ are delayed to become ■'■', and are applied to the transistors Q10 and Q11. Transistor Q16, Q1
7 have their bases connected to terminals 12a and 12b, respectively,
Its emitter is connected to the base of transistor Q15 and constant current source 16, and to the base of transistor Q14 and constant current source 17.
It is connected to the. A flip-flop 18 is configured by transistors Q10 to Q17 and resistors RL1 and RL2.

[0017] When the head 3 is not disconnected,
When the terminal 1a is high, the transistor Q10 is turned on by the high voltage ■', the transistor Q13 is turned on, the transistor Q12 is turned off, and the terminal 12a is high.
, the terminal 12b becomes L. At this time, transistor Q1
The emitter of transistor Q17 is high, and the emitter of transistor Q17 is low.
becomes. On the other hand, when the terminal 1b becomes H, the transistor Q10 is turned off by the voltage ■' L, so the transistors Q13 and Q12 are turned off. On the other hand, the transistor Q15 is turned on as the transistor Q11 is turned on by the voltage ■' H. (The emitter of transistor Q16 is high
), transistor Q14 is off (transistor Q
The emitter of 17 becomes (by L), and the terminal 12a becomes H,
Terminal 12b remains at L.

Next, when the head 3 is disconnected and the terminal 1a is at H, the transistor Q12 is turned on by turning on the transistor Q10 due to the H voltage.
The transistor Q13 is turned off (because ■>■), and the terminal 12a becomes L and the terminal 12b becomes H. At this time, the emitter of transistor Q16 becomes L, and the emitter of transistor Q17 becomes H. On the other hand, when the terminal 1b is H, the transistor Q14 is turned on (the emitter of the transistor Q17 is turned on by the H) as the transistor Q11 is turned on due to the H voltage, and the transistor Q15 is turned off, and the terminal 12a is L and the terminal 12b is turned on. It remains H.

In this embodiment, in FIG. 1, the voltage between ■ and ■,
Using the voltage between ■ and ■ of the voltage between ■, turn on and off transistors Q12 and Q13 to terminals 12a and 12b.
This state is maintained by the transistors Q14 to Q17 even during the next switching period of the voltages (1) and (2). Therefore, if the switching of voltages ■ and ■ is made to coincide with the switching of voltages ■ and ■, switching will occur when the states of transistors Q12 and Q13 are uncertain (at the time of switching). Output terminal 12a,
Since the polarity of 12b is not determined and the operation becomes unstable, in this embodiment, delay circuits 151 and 152 are installed to control the voltages ■,
The voltage ■'■' is switched after the level of (2) is determined.

[0020]

According to the present invention, since the output transistor is simply switched according to the base-emitter voltage of the head current supply transistor, head disconnection can be avoided regardless of the frequency of write data. Presence can be detected reliably.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is an operational waveform diagram in the present invention.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

FIG. 4 is a block diagram of a general recording/reproducing circuit.

FIG. 5 is a configuration diagram of an example of a conventional circuit.

FIG. 6 is an operational waveform diagram in a conventional example.

FIG. 7 is a waveform diagram illustrating problems in the conventional example.

[Explanation of symbols]

1a, 1b Write data input terminal 2 Write driver 3 Thin film head 10, 10' Head disconnection detection circuit 11, 16, 17 Constant current source 12a, 12b Output terminal 151, 152 Delay circuit 18 Flip-flop Q1 to Q4 Switching transistor Q5
~Q6 Head current supply transistor Q10, Q
11, Q16, Q17 Transistors Q12 to Q15
output transistor

Claims (3)

[Claims] Claim 1: A pair of switching transistors (Q1 and Q3, Q
2 and Q4 ), and the pair of switching transistors (Q1
By the output of the write driver (2), which is provided with a pair of head current supply transistors (Q5 and Q6) that supply current to the recording/reproducing head (3) by turning on and off Q3, Q2, and Q4). In the head disconnection detection circuit for detecting the presence or absence of disconnection in the recording/reproducing head (3), the pair of switching transistors (Q1
an output section having output transistors (Q12 to Q15) that are turned on and off by the base-emitter voltage of the head current supply transistors (Q5, Q6) according to the on and off states of the head current supply transistors (Q5, Q6); , and output terminals (12a, 12b) for obtaining detection outputs from the collectors of the output transistors (Q12 to Q15). 2. The output section has respective bases connected to the bases and emitters of the head current supply transistors (Q5, Q6), and emitters connected in common,
Two sets of output transistors (Q12 and Q13, Q
14 and Q15) and the two sets of output transistors (Q12
and Q13, Q14, and Q15), and are turned on and off by the write data, and have their emitters commonly connected to the current source (11). 2. A head disconnection detection circuit according to claim 1, wherein said head disconnection detection circuit comprises: 3. The output section includes a pair of delay circuits (151, 152) that delay the write data for a predetermined period of time.
A pair of switching transistors (Q10, Q1) are turned on and off by the output of the delay circuits (151, 152), and have their emitters commonly connected to the current source (11).
1) and the head current supply transistor (Q5,
A pair of transistors having their respective bases connected to the base and emitter of Q6), whose emitters are commonly connected to one of the pair of switching transistors (Q10), and whose collectors are connected to the output terminals (12a, 12b). is connected to the first output transistors (Q12, Q13), the other of the pair of switching transistors (Q11), and the respective collectors of the first output transistor (Q12, Q13); When one of the transistors (Q10) is on, the output terminal (12a,
2. The head disconnection detection circuit according to claim 1, further comprising second output transistors (Q14 to Q17) that maintain the output state of the head disconnection detection circuit (12b).