JPH04239723A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPH04239723A
JPH04239723A JP3006146A JP614691A JPH04239723A JP H04239723 A JPH04239723 A JP H04239723A JP 3006146 A JP3006146 A JP 3006146A JP 614691 A JP614691 A JP 614691A JP H04239723 A JPH04239723 A JP H04239723A
Authority
JP
Japan
Prior art keywords
insulating film
etching
interlayer insulating
step portion
interlayer insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3006146A
Other languages
English (en)
Inventor
Hidekazu Nakano
仲野　英一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3006146A priority Critical patent/JPH04239723A/ja
Priority to EP92300574A priority patent/EP0496614A1/en
Publication of JPH04239723A publication Critical patent/JPH04239723A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に自己整合的にコンタクトホールを開口する方
法に関するものである。
【０００２】
【従来の技術】従来技術によって自己整合的にコンタク
トホールを形成する方法について、図２（ａ），（ｂ）
を参照して説明する。
【０００３】はじめに図２（ａ）に示すように、シリコ
ン基板１上にポリシリコン２および酸化膜３からなる素
子によって段差が形成されている。
【０００４】つぎに段差形状を保存するように層間絶縁
膜４を堆積し、段差の凹部にまたがる開口を有するフォ
トレジスト６のパターンを形成する。
【０００５】つぎに図２（ｂ）に示すように、反応性イ
オンエッチングなどにより開口に露出した層間絶縁膜４
を異方性エッチングして、コンタクトホールを自己整合
的に形成することができる。
【０００６】
【発明が解決しようとする課題】従来技術において自己
整合的にコンタクトホールを形成するためには、コンタ
クトホールとして開口する領域に必ず段差によって形成
された凹部が必要である。通常この凹部はコンタクトホ
ールを開口しない領域にも存在する。
【０００７】このコンタクトホールを開口しない領域に
おける段差は金属配線形成後も保存され、さらに上層配
線を形成する際に段切れによるオープンや、凹部への配
線金属の残渣による配線間のショートの原因になる。
【０００８】
【課題を解決するための手段】本発明の半導体装置の製
造方法は、素子が形成された半導体基板の一主面上に、
前記素子の段差形状を保存する第１の層間絶縁膜を堆積
する工程と、全面に第２の層間絶縁膜を段差を埋設する
ように堆積する工程と、前記第１の層間絶縁膜の段差領
域に開口を有するフォトレジストパターンを形成する工
程と、前記開口に露出した前記第２の層間絶縁膜を前記
第１の層間絶縁膜に対して選択比の高い条件でエッチン
グする工程と、前記開口に露出した前記第１の層間絶縁
膜をエッチングする工程とを有するものである。
【０００９】
【実施例】本発明の一実施例について、図１（ａ）〜（
ｃ）を参照して説明する。
【００１０】はじめに図１（ａ）に示すように、シリコ
ン基板１上に、ポリシリコン２および酸化膜３からなる
素子を形成したのち、減圧ＣＶＤ法により第１の層間絶
縁膜となる酸化膜４を堆積する。
【００１１】つぎに常圧ＣＶＤ法により第２の層間絶縁
膜となるＢＰＳＧ膜５を堆積し、９５０℃の窒素雰囲気
で熱処理を行なって下地の段差を埋設してからフォトレ
ジスト６からなるマスクパターンを形成する。
【００１２】つぎに図１（ｂ）に示すように、ＣＦ４　
および酸素（Ｏ２　）からなる混合ガスプラズマにおい
て、総ガス流量を４００ｓｃｃｍ、Ｏ２　の分圧を１０
％、圧力を１Ｔｏｒｒに制御した平行平板型電極構造の
反応室内で陽極側に高周波電力を印加して、第１のエッ
チングを行なう。
【００１３】このとき第２の層間絶縁膜であるＢＰＳＧ
膜５のエッチング速度は第１の層間絶縁膜である酸化膜
４のエッチング速度の１．３倍以上になるように、エッ
チング条件が設定されている。
【００１４】つぎに図１（ｃ）に示すように、ＣＦ４　
および水素からなる混合ガスプラズマにおいて、総流量
を１００ｓｃｃｍ、水素の分圧を１０％、圧力を５０ｍ
Ｔｏｒｒに制御した第１のエッチングと同一の反応室内
で、陰極に高周波電力を印加して、第２のエッチングを
行なって段差の凹部に自己整合的に形成されたコンタク
トホールが得られる。
【００１５】本実施例において第１の層間絶縁膜として
用いた酸化膜の代りに、窒化膜あるいはＳｉＯＮ膜を用
いることができる。第２の層間絶縁膜として用いたＢＰ
ＳＧ膜の代りに、ＰＳＧ膜、ポリイミドなどの有機膜、
あるいは有機ガラス膜を用いても同様の効果を得ること
ができる。
【００１６】また第１の層間絶縁膜および第２の層間絶
縁膜のエッチングに、Ｃ２　Ｆ６　、Ｃ３　Ｆ８　、Ｃ
ＨＦ３　、Ｃ２　Ｈ２　Ｆ、Ｃ３　ＨＦ７　、Ｃ３　Ｈ
２　Ｆ６　、Ｃ３　Ｈ３　Ｆ５　などのフルオロカーボ
ンやＯ２　、Ｎ２　、Ｈｅ、Ａｒ、Ｈ２　などを組合わ
せた混合ガス系プラズマを用いることもできる。
【００１７】さらに第１の層間絶縁膜および第２の層間
絶縁膜のエッチング工程で平行平板型の代りに同軸型あ
るいはダウンフロー型のプラズマエッチング装置、もし
くは平行平板型、ＥＣＲ放電型、磁場印加型の反応性イ
オンエッチング装置を兼用あるい工程毎に異なる装置を
用いることもできる。
【００１８】
【発明の効果】自己整合的なコンタクトホールの形成工
程において、段差による凹部を完全に平坦化することが
できる。
【００１９】その結果上層配線工程での段切れによるオ
ープンや、エッチング残渣による配線ショートを防止す
る効果がある。
【００２０】さらに第２の層間絶縁膜を第１の層間絶縁
膜に対して選択比の高い条件でエッチングしたのち、第
１の層間絶縁膜をエッチングしている。そのためコンタ
クトホール形成工程における自己整合性を損なうことが
ない。
【図面の簡単な説明】
【図１】本発明の第１の実施例を工程順に示す断面図で
ある。
【図２】従来技術によるコンタクトホールの自己整合的
な形成方法を工程順に示す断面図である。
【符号の説明】
１　　　　シリコン基板 ２　　　　ポリシリコン ３　　　　酸化膜 ４　　　　酸化膜 ５　　　　ＢＰＳＧ膜 ６　　　　フォトレジスト

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】　　素子が形成された半導体基板の一主面
    上に、前記素子の段差形状を保存する第１の層間絶縁膜
    を堆積する工程と、全面に第２の層間絶縁膜を段差を埋
    設するように堆積する工程と、前記第１の層間絶縁膜の
    段差領域に開口を有するフォトレジストパターンを形成
    する工程と、前記開口に露出した前記第２の層間絶縁膜
    を前記第１の層間絶縁膜に対して選択比の高い条件でエ
    ッチングする工程と、前記開口に露出した前記第１の層
    間絶縁膜をエッチングする工程とを有することを特徴と
    する半導体装置の製造方法。
JP3006146A 1991-01-23 1991-01-23 半導体装置の製造方法 Pending JPH04239723A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3006146A JPH04239723A (ja) 1991-01-23 1991-01-23 半導体装置の製造方法
EP92300574A EP0496614A1 (en) 1991-01-23 1992-01-23 Method for forming contact hole in process of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3006146A JPH04239723A (ja) 1991-01-23 1991-01-23 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPH04239723A true JPH04239723A (ja) 1992-08-27

Family

ID=11630385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3006146A Pending JPH04239723A (ja) 1991-01-23 1991-01-23 半導体装置の製造方法

Country Status (2)

Country Link
EP (1) EP0496614A1 (ja)
JP (1) JPH04239723A (ja)

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JPH07263554A (ja) * 1994-03-25 1995-10-13 Nec Corp 半導体装置及びその製造方法
JPH08293487A (ja) * 1995-04-24 1996-11-05 Nec Corp エッチング方法
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Cited By (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07263554A (ja) * 1994-03-25 1995-10-13 Nec Corp 半導体装置及びその製造方法
JPH08293487A (ja) * 1995-04-24 1996-11-05 Nec Corp エッチング方法
WO1998036449A1 (fr) * 1997-02-12 1998-08-20 Daikin Industries, Ltd. Gaz d'attaque et de nettoyage
US6905980B2 (en) 1999-03-09 2005-06-14 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing same
JP2002203900A (ja) * 2000-12-11 2002-07-19 Hynix Semiconductor Inc 半導体装置のコンタクト孔及びスペーサ形成方法
JP2008300616A (ja) * 2007-05-31 2008-12-11 Nippon Zeon Co Ltd エッチング方法
JP2009152550A (ja) * 2007-10-22 2009-07-09 Applied Materials Inc 少なくとも１つの誘電体層を形成するための方法およびシステム
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US9236266B2 (en) 2011-08-01 2016-01-12 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
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