JPH0424120U - - Google Patents
Info
- Publication number
- JPH0424120U JPH0424120U JP6556990U JP6556990U JPH0424120U JP H0424120 U JPH0424120 U JP H0424120U JP 6556990 U JP6556990 U JP 6556990U JP 6556990 U JP6556990 U JP 6556990U JP H0424120 U JPH0424120 U JP H0424120U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- latch
- reset
- type latch
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000002265 prevention Effects 0.000 description 1
Description
第１図は本考案の実施例の回路図、第２図はハ
ザード防止回路の回路図、第３図は同上の動作説
明用タイムチヤート、第４図は従来例の回路図、
第５図は同上の動作説明図である。
ＩＣ１〜ＩＣ３はＤ型ラツチ回路、ＩＣ１０は
論理積回路、ＲＥＳＥＴは外部リセツト信号、Ｒ
ＥＳはリセツト信号である。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a hazard prevention circuit, Fig. 3 is a time chart for explaining the operation of the same, Fig. 4 is a circuit diagram of a conventional example,
FIG. 5 is an explanatory diagram of the same operation as above. IC1 to IC3 are D-type latch circuits, IC10 is an AND circuit, RESET is an external reset signal, and R
ES is a reset signal.
Claims (1)
を行なわせるためのリセツト回路において、同じ
クロツクを同期して入力する複数のＤ型ラツチ回
路からなり、前段のラツチ出力を後段のラツチ入
力とするように各Ｄ型ラツチ回路を従属接続する
ともに、１段目のＤ型ラツチ回路のリセツト端子
に外部リセツト信号を接続し且つ当該Ｄ型ラツチ
回路のラツチ入力を“Ｈ″に固定して形成された
遅延回路と、上記各Ｄ型ラツチ回路のラツチ出力
を入力して論理積演算を行う論理積回路とを備え
、該論理積回路の出力をリセツト信号とすること
を特徴とするリセツト回路。 A reset circuit for system initialization of a microprocessor consists of a plurality of D-type latch circuits that synchronously input the same clock, and each D-type latch circuit is connected so that the latch output of the previous stage is used as the latch input of the latter stage. A delay circuit formed by connecting latch circuits in a subordinate manner, connecting an external reset signal to the reset terminal of the first stage D-type latch circuit, and fixing the latch input of the D-type latch circuit to "H"; A reset circuit comprising an AND circuit which inputs the latch outputs of each of the D-type latch circuits and performs an AND operation, and uses the output of the AND circuit as a reset signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6556990U JPH0424120U (en) | 1990-06-21 | 1990-06-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6556990U JPH0424120U (en) | 1990-06-21 | 1990-06-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0424120U true JPH0424120U (en) | 1992-02-27 |
Family
ID=31597515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6556990U Pending JPH0424120U (en) | 1990-06-21 | 1990-06-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0424120U (en) |
-
1990
- 1990-06-21 JP JP6556990U patent/JPH0424120U/ja active Pending