JPH04242940A - Manufacture of heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE:To facilitate etching and to improve high frequency characteristics by forming a thick layer to lead out an electrode in addition to a thin base layer before a base electrode forming face is exposed. CONSTITUTION:An n<+>GaAs 2, an n<->GaAs layer 3, and an insulating layer 20 are piled up on a semiinsulating GaAs substrate 1. The insulating layer 20 is removed by using an emitter mask. With a remaining insulating layer as a mask, the n<->GaAs layer 3 is removed for implantation of oxygen ions. A high-doped p-type GaAs layer is epitaxially grown on the n<->GaAs layer 2 at a zone implanted with oxygen ions. The masking insulating layer is removed, and a P<++>GaAs layer 4 serving as the base is grown. Next, an undoped GaAs layer (spacer)5, an n<+>AlGaAs layer (emitter)6, and an n<++>InGaAs layer 7 are piled up. Therefore, before the base layer 4 is exposed to form a base electrode, a thick p<++> layer is formed in contact with the base layer 4 in addition to the high-doped GaAs layer, so that it is easy to a lead out base electrode.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor (hereinafter referred to as an HBT), and more particularly to an HBT that is easier to manufacture and has improved performance.

0002

2. Description of the Related Art FIGS. 2(a) to 2(g) schematically show the manufacturing process of a conventional HBT. The process will be explained step by step. (a) First step An n+ GaAs layer 2 with a thickness of 0.4 μm and an impurity concentration of 5×10 18 cm −3 is formed on a semi-insulating GaAs substrate 1, with a thickness of 0.
．． 4μm, impurity concentration 5×1016cm-3 n-G
aAs layer 3, thickness 0.1 μm, impurity concentration 3×1019
cm-3 p+ GaAs layer 4, 0.01 μm thick G
aAs undoped layer 5, thickness 0.2 μm, impurity concentration 1
×1018 cm-3 n+ AlGaAs layer 6, thickness 0
．． 16μm, impurity concentration 5×1018cm-3 n+
GaAs layers 7 are sequentially stacked. (b) Second step: An Al layer 8 is formed on the n+ GaAs layer 7 on the surface by vapor deposition or the like, and this Al layer is etched leaving the parts where the emitter and base are to be formed, and the remaining Al layer 8 is masked. Oxygen ion as 200KeV, 1×1015cm-3
It is insulated by implanting up to n-GaAs (collector layer) 3 at a certain level. (c) Third step Al layer 8 is removed and oxide film SiOx 9 and Al layer 8 are removed.
After that, the oxide film SiOx 9 and the Al layer 8a are removed, leaving only the portion where the emitter electrode and the base electrode are to be formed. (d) Fourth step wet etching removes n+ GaAs layer 7, n+
Remove the AlGaAs layer 6 and the undoped GaAs layer 5,
The p+GaAs layer 4, which is the base layer, is exposed. As a result, the layer below the oxide film SiOx 9 is under-etched. Thereafter, oxygen ions are implanted into the base p+ GaAs layer 4 and below at 200 KeV and about 2×10 13 cm −3 and annealing is performed at 750° C. for 10 seconds to restore crystallinity. These oxygen ions penetrate the p+ GaAs layer 4 and reach the n- GaAs layer (collector) 3, and this n-
The GaAs layer is insulated, and the p+ GaAs layer 4 and n+
This contributes to reducing the capacitance between the GaAs layers 2. (e) Fifth step: Remove the Al layer 8a, apply a resist 10, remove the resist at the location where the collector electrode is to be formed by photolithography, and remove the p+ GaAs from the removed portion.
Remove layer 4 and n-GaAs layer 3. (f) Sixth step The oxide film SiOx 9 is removed, the emitter electrode 11 and the collector electrode 12 are formed by vapor deposition, etc., and the resist 10
After removing the
Inject H+ ions around the BT. (g) Seventh step: The base electrode 13 is formed by self-alignment.

0003

[Problems to be Solved by the Invention] In step (d) of the above-mentioned conventional HBT using GaAs, the base layer exposure etching for taking out the base electrode is performed while taking into consideration the type and thickness of the thin film. It is necessary to control the thickness on the order of close to 0.01 μm by adjusting the concentration of the liquid and further adjusting the etching time. However, it is difficult to etch to the desired depth (stop the etching the moment the base layer 4 appears) at once, and there are variations in the etching depth on the wafer, so it is necessary to remove it little by little while monitoring the amount of etching. There was a problem that it had to be done. Furthermore, there is a problem in that an excessively etched HBT has a large base resistance, making it difficult to provide good high frequency characteristics.

The present invention has been made to solve the problems of the prior art described above, and after forming a part of the collector layer in a region that does not contribute to the function of the HBT as a base layer in advance,
By forming a thin, high-concentration base layer that includes that part and contributes to the function of the HBT, it is possible to facilitate the extraction of the base electrode, lower the base resistance, and improve high frequency characteristics. With the goal.

[0005]

[Means for Solving the Problems] The structure of the present invention for solving the above-mentioned problems of the prior art includes a collector (n- layer) and a base (p-layer) made of GaAs layers on a semi-insulating GaAs substrate.
++ layer) and an emitter layer made of AlGaAs by epitaxial growth, there are two steps: stacking an insulating layer after forming the collector layer, and patterning the insulating layer using an emitter mask. a step of slightly etching away the surface of the exposed portion of the collector layer using the insulating layer as a mask; and a step of implanting oxygen ions into the collector layer using the insulating layer as a mask;
A step of selectively epitaxially growing the high concentration p-type GaAs layer to a thickness equivalent to etching away the portion into which oxygen ions have been implanted using the insulating layer as a mask, and removing the insulating layer to expose the n- layer. a step of thinly laminating a p++ type GaAs layer on the substrate including the exposed n- layer and the p++ type GaAs layer;
The method is characterized in that it includes a step of laminating an undoped GaAs layer and an emitter layer on the aAs layer.

[0006]

[Function] The thick base layer is formed in the area other than the insulating layer masked with the emitter mask and forms the external base area from which the electrode is taken out, and the thin base layer is the collector layer with the insulation removed. It is formed on top of the base and becomes a functional part.
Even if the base is made extremely thin, it is easy to take out the base electrode.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1(a) to 1(g) are sectional views showing schematic manufacturing process diagrams showing one embodiment of the present invention. The process will be explained step by step. (a) First step N+ as a contact layer on the semi-insulating GaAs substrate 1
GaAs layer (thickness 0.4 μm, impurity concentration 5×101
8cm-3) 2 and n-GaAs layer (thickness 0.4
μm, impurity concentration of about 5 x 1016 cm-3) 3, and then an insulating layer of about 1 μm (SiO2 or Si3N).
4, etc.) 20 are stacked. (b) Second step Photolithography and etching are performed using an emitter mask (not shown) to remove the insulating layer 20 and remove the insulating layer other than the mask portion. (c) Third step Using the remaining insulating layer 20 as a mask, the n-GaAs layer 3 is removed by about 0.2 μm by wet etching. (d) Fourth step: Oxygen ions are added at 100K using the insulating layer 20 as a mask.
Inject at eV to about 5×10 13 cm −3 . (e) Fifth step CBE (Chemical Beam Epitaxy)
) etc. in the part where oxygen ions were implanted using a device such as
A high concentration p-type (about 1021 cm-3) GaAs layer is selectively epitaxially grown on the GaAs layer 2 using TMG (trimethyl gallium) or the like. (f) 6th process The insulating layer of the mask is removed and the p++G becomes the base of the HBT.
The aAs layer 4 is regrown to a thickness of 0.05 μm or less in the same manner as described above. (g) Seventh step Next, an undoped GaAs layer 5 with a thickness of about 0.01 μm, a thickness of 0.2 μm, and an impurity concentration of 1×10 18 cm −3
n+ AlGaAs layer 6 with a thickness of about 0.1 μm, and an n+ GaAs layer 0 with an impurity concentration of about 1×10 18 cm −3
thickness 0.05μm, impurity concentration 1×1019cm-3
n++ InGaAs 7 are sequentially laminated. The subsequent steps are the same as those shown in FIGS. 2(b) to 2(g) of the conventional example to complete the HBT, but in the process of the present invention, the steps shown in FIG. 2(d)
In the process shown in , when the base layer 4 is exposed and a base electrode is formed, in addition to the 0.05 μm thickness that functions as an HBT, a 0.2 μm thick layer that is in contact with the base layer 4 is prepared in advance. Since the p++ layer is formed, the base electrode can be easily taken out even if the base is simply made thinner than in the conventional case. As a result, H with excellent frequency characteristics
BT can be realized. Note that the insulating layer 2 of the mask
When forming 0, the emitter mask can be used, so there is no increase in mask manufacturing cost.

[0008]

[Effects of the Invention] According to the present invention, as specifically explained in conjunction with the embodiments above, when exposing the base electrode forming surface, in addition to the thin base layer, a thick layer for taking out the electrode is formed in advance. This makes it possible to facilitate etching and improve high frequency characteristics.

[0009]

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic manufacturing process of an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic manufacturing process of a conventional example.

[Explanation of symbols]

1 Semi-insulating GaAs substrate 2 n+ GaAs layer 3 n- GaA layer 4 p++ GaAs layer 5 GaAs undoped layer 6 n+ AlGaAs layer 7 n++ InGaAs/n+ GaAs layer 20
insulation layer

Claims (1)

[Claims] 1. A heterojunction bipolar transistor manufactured by epitaxially growing a collector (n- layer) made of a GaAs layer, a base (p++ layer), and an emitter layer made of AlGaAs on a semi-insulating GaAs substrate. , a step of laminating an insulating layer after forming the collector layer, a step of patterning the insulating layer using an emitter mask, and a step of slightly patterning the surface of the exposed portion of the collector layer using the insulating layer as a mask. a step of removing by etching, a step of implanting oxygen ions into the collector layer using the insulating layer as a mask, and a step of removing the high-concentration p-type GaAs layer by etching the portion into which oxygen ions were implanted using the insulating layer as a mask. a step of selectively epitaxially growing the n- layer to a thickness of
− layer and a p++ type GaAs layer on a substrate including a p++ type GaAs layer and a p++ type GaAs layer.
A method for manufacturing a heterojunction bipolar transistor, comprising the steps of: laminating a thin aAs layer; and laminating an undoped GaAs layer and an emitter layer on the p-type GaAs layer.