JPH04243316A - Start timing setting changeover system for pulse signal - Google Patents

Abstract

PURPOSE:To reduce the time and cost for setting a pulse start timing by providing a selector to switch the setting a pulse start timing just after each of n-bit count signal registers (in total n-sets). CONSTITUTION:When a pulse of logical '1' whose width is one period (1T) is inputted to a terminal DIN, '0' is fetched to count signal registers 11-14 from a terminal CIN. When a succeeding clock pulse is inputted to each register, since the input to the terminal DIN is zero, count is started in a count circuit 1. Thus, when a clock pulse of a count number set by a pulse start timing setting circuit 2 is inputted to the terminal CIN, '0' is outputted as a set signal 25. Then a pulse signal hold register 31 is set to '1' and holds the reset signal 26 till it is '0'. That is, a pulse start timing from an output terminal DOUT is set to an optional value up to 1T-16T after the input by selecting any of timing setting signals S0-S3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal start timing setting switching system.

0002

2. Description of the Related Art Conventionally, in this type of pulse start timing setting switching system, when one timing is selected from four types of pulse start timing settings, a count signal register 41 is used as shown in FIG. 2 (or FIG. 3). ~ 44 - In a circuit configured in the order of NAND circuits 51 to 54 - selector 55, pulse start timing setting signal input pin 5
According to the 2-bit pulse start timing setting signal input from 7, one type is selected from four types of pulse start timing signals S0 and S1 prepared in advance in anticipation of possible settings.

0003

The conventional pulse start timing setting switching system described above has the following drawbacks.

In the pulse start timing setting switching circuit shown in FIG. 2, it is necessary to predict four possible timings in advance and prepare a circuit for selecting one of the four timings. Therefore, it takes time and money to predict possible pulse start timings or to configure a circuit to select one type of value from the expected pulse start timings. Furthermore, if it becomes necessary to set a pulse start timing that was not expected, or if it is impossible to predict the pulse start timing that needs to be set in advance, it cannot be handled.

In addition, there is a circuit based on the pulse start timing setting switching circuit shown in FIG. 2, which is configured so that the setting timing can be set to any value between 0 and above (2 to the n power) - 1 using the count value of a counter. 3 (the example in FIG. 3 is n
=4), the circuit becomes quite complex and the number of stages of NAND circuits and selectors increases, increasing the probability of circuit malfunction due to gate failure and power consumption.

[0006]

[Means for Solving the Problems] The pulse start timing setting switching method of the present invention includes an n-bit counter that can count up to (2 to the n power) -1, and an n-bit count signal register immediately after the counter. A set of n selectors in total, an n-bit select signal that switches the pulse start timing setting, a pulse signal hold circuit that outputs the set pulse signal, and a pulse signal hold circuit from the output of each selector. It has a NAND circuit that generates a signal and a NAND circuit that generates a reset signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the figure, 1 is a counter circuit, 11 to 14 are count signal registers, 2 is a pulse start timing setting circuit, and 21 to 14 are count signal registers.
24 is a pulse start timing setting switch selector, 25 is a pulse signal hold register set signal generated by NAND of the output of each selector, 26 is a pulse signal hold register reset signal, 3 is a pulse signal hold circuit, 31 is a pulse signal Hold register, terminal CI
N is a clock pulse input pin, where one period of the clock pulse is expressed as 1T, the following two periods are expressed as 2T, the third period is expressed as 3T, and so on, and the n period is expressed as nT.

In this embodiment, 1T from the terminal DIN
When the width logic "1" is a pulse input, the count signal registers 11 to 11 are input by clock pulse input from CIN.
14 is loaded with "0". When the next clock pulse input enters each register, the input of the terminal DIN is “0”.
”, so when the count circuit 1 starts counting and the clock pulses of the count number set in the pulse start timing setting circuit 2 are input from the terminal CIN, the pulse signal hold register set signal 25 is set as “ 0" is output, the contents of the pulse signal hold register 31 become "1", and the pulse signal hold register 31 is held until the timing when the reset signal 26 becomes "0".

Therefore, for example, the start of the pulse can be
When outputting a pulse signal that ends 5T and 16T after the N input, set the pulse start timing setting signals S0, S1, S2, and S3 to "0" and ", respectively.
1”, “0”, and “0”, and set 1 to terminal DIN.
When a pulse of "1" with T width is input, the number of clock pulse inputs is counted from the next clock pulse, and the number of clock pulse inputs is 4T.
After that, the pulse signal hold register set signal 25 becomes “
0'', the pulse signal hold register 31 is set after 5T, and the pulse signal hold register 31 is set after 15T.
The pulse signal hold register 31 is reset 16T after the reset signal 26 becomes "0".

That is, the pulse start timing setting signal S0
, S1, S2, and S3, the terminal D
The timing of the start of the pulse signal from OUT can be set to any value from 1T to 16T after the pulse input to the terminal DIN.

0012

[Effects of the Invention] As explained above, the present invention provides the following effects by providing a total of n selectors for switching the pulse start timing setting, one immediately after the n-bit count signal register. .

With the pulse start timing setting switching circuit shown in FIG. 2, there is no need to predict in advance the values that may be set as the pulse start timing, and the time cost for this can be reduced. Furthermore, it is possible to deal with cases where it is necessary to set a pulse start timing that was not expected, or cases where prediction cannot be made in advance.

Regarding the pulse start timing setting switching circuit shown in FIG. 3, the number of selector stages and the number of NAND gates can be significantly reduced, and a circuit with the same function can be constructed using a very simple circuit, so malfunctions due to gate failure can be avoided. The probability of this and power consumption can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a first conventional example.

FIG. 3 is a circuit diagram showing a second conventional example.

[Explanation of symbols]

1 Counter circuit 3 Pulse signal hold circuits 11-14 Count signal registers 20-25
Selector 100 input pin

Claims (1)

[Claims] 1. A total of n selectors for switching the pulse start timing setting are provided, one immediately after the n-bit count signal register, and the pulse signal start timing is set by the n-bit select signal for switching the selector. A pulse signal start timing setting switching method that allows the count value to be set to any value from 0 to (2 to the nth power) - 1 or less.