JPH0424862A - Inter-processor fault detection system - Google Patents

Abstract

PURPOSE:To completely check a conflict control circuit by providing a means which checks the coincidence of contents between the execution suppression information generated in each processor and the suppression information transferred among the processors. CONSTITUTION:When a memory request is produced and the conflict control is carried out, the negative logic output 118 of a priority F/F 102 of a processor 1 is set at '1' and '1' is outputted to an own system execution suppression signal 115 serving as the output of an AND gate 107. The signal 115 is sent to a processor 2. The processor 2 has a collation preference execution signal 220, i.e., the output of an AND gate 209 kept at '1' since an execution grant signal 214 and a request signal 111 are kept at '1'. The signal 220 is inputted to a coincidence detection circuit 208 together with the signal 115 of the processor 1. The processor 1 has the same circuit constitution as the processor 2. Thus a conflict control circuit is completely checked.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault detection method for processing devices, and particularly to a fault detection method between processing devices that issue processing requests to shared resources.

[Conventional technology]

Conventionally, there is a failure detection method between processing devices in which two processing devices issue processing requests to a shared resource, and the two processing devices mutually send processing request information for the shared resource to suppress any processing request. No fault detection circuit or the like was provided to check for logical contradictions in competing circuits when two processing units competed with each other.

[Problem to be solved by the invention]

In the conventional technology described above, processing request information for shared resources exchanged between image processing devices, contention prevention circuits within each processing device, etc. are not checked at all, and if a failure occurs in these circuits, the shared resources are Processing requests for resources may be sent out at the same time from the image processing device, or in the event of contention, no processing requests may be issued at all.As demands for the reliability of processing devices are increasing today, reliability is greatly reduced. It has the disadvantage that it does.

[Means to solve the problem]

In the fault detection method between processing devices of the present invention, two processing devices issue a processing request to a shared resource, and the respective processing devices mutually send processing request information for the shared resource. In a failure detection method between processing devices that suppresses a processing request, means for mutually sending execution suppression information generated when a processing request for a shared resource conflicts between the respective processing devices; and a means for detecting whether or not the content of the execution inhibition information generated within the system matches the content of the inhibition information sent to each other.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, 1 is the processing bag W (I), 2 is the processing device (II)
, 3 indicates the main memory, and the processing units (I), (It) 1
．． 2 makes a memory access request to the main storage device 3, which is a mutually shared resource, and the processing units (I) and (I[>
1.2 configurations are completely equivalent.

Priority order F/F10 in processing devices (I) and (II) 1.2
Reference numerals 2 and 202 denote F/Fs that give priority to hold conditions, and initial values of "1pa" and "0'° are set in advance, respectively, and are used to determine the priority order in the event of contention.

These operations will be explained with reference to the drawings.

First, a case where a memory access request to the main storage device 3 is generated only from the processing device (I) 1 will be described.

When a memory access request is generated within the processing device (1) 1, a memory access request signal 110 sent from a main processing unit (not shown) becomes "1", and the request F/F 101 is set to "1".

The request signal 111, which is the output of the request F/F 101, becomes "1°" and is input to the AND gates 104 and 105. Here, since no memory request request is generated only from the processing device (I), the request signal 111 is output from the processing device (■) 2. The request F/F 201 within is still set to "0", and therefore the request signal 211 is also "O'°".

Therefore, the other input of the AND gate 105 becomes "0'", so the output signal 113 of the AND gate 105 becomes "0P", and furthermore, the execution permission signal 114, which is the output signal of the Nant gate 106, becomes "1'" and the AND gate The output of 104 will be determined only by the value of request signal 111.

Therefore, the memory request signal 112, which is the output of the AND gate 104, becomes 1'' at this time, and a memory request is issued to the main memory device M3.

At the same time, the memory request signal 112 is sent to the main processing unit, and the memory access request signal 110 becomes "0".

be drowned.

Next, a case where memory access requests conflict between the processing devices (I) and (If) 1.2 will be described.

When the memory access request signals 110 and 210 of the processing units (I) and (II) 1.2 become "1" at the same time, the request F/FIOL and 201 are each set to "1", and the request signals 111 and 112 are set to "1". "1' is output. These signals are processed by a processing device (II), respectively;
(I) It is output in 2.1.

Therefore, in the processing device (■〉1), the AND gate 10
5 inputs each become "1", and the output signal 113 becomes "1".
is output.

Here, the positive logic output 117 of the priority F/F 102 is 1°
”, the execution permission signal 114, which is the output of the Nant gate 106, is output as 'O°°' and the AND gate 1
Since the output of 04 is suppressed, the memory request signal 11
2, "0°" is output. In other words, processing bag f(I)1
memory access requests are suppressed.

On the other hand, in the processing device (■) 2, priority order F/F 202
Since the positive logic output 217 of the Nant gate 206 is “0”, the execution conflict signal 214 which is the output of the Nant gate 206 is “1”.
', the memory request signal 212 which is the output of the AND gate 204 becomes 1, a memory request is issued, and competition control is performed.

At this time, the negative logic output 118 of the priority F/F 102 of the processing device (■) 1 is "1'", and the own system execution inhibition signal 115, which is the output of the 7nd gate 107, is "°°l".
will be presented. In other words, this indicates that self-system execution is inhibited when main memory access requests conflict between two processing devices (I>1.(II)2).

This self-system execution inhibition signal 115 is the processing bag W (II)2
sent to. In the processing device (■) 2, the execution permission signal 214
is “loo” and the request signal 111 is also “1”.
'', the matching priority execution signal 220, which is the output of the AND gate 209, becomes 1, and the -number construction circuit 208
is input together with the self-system execution inhibition signal 115 of the processing device (I>1), and a match is detected.

Since both signals are "1" here, the coincidence detection circuit 20
The output 216 of 8 is "o" and the fault indication F/
"0°' is set in F203.

The processing device (■) 1 also has a circuit configuration similar to the above, but in this case, the self-system execution inhibition signal 215 of the processing device (■) 2 is output as '0'', and the contention priority execution signal 12 is output.
0 becomes O°' and is input to the coincidence detection circuit 108, its output 116 becomes "0", and the fault display F/F 103 is set to "0"°.

In the circuit configuration described above, a failure occurs in the execution inhibiting logic or execution permitting logic of each processing device at the time of contention, and memory requests of each processing device are issued simultaneously. Alternatively, if memory requests are to be suppressed at the same time, it is an input signal to the minus number output circuits 108 and 208. Self-system execution suppression signal 115, 215 conflict priority execution signal 1
1 o.

120, a failure display F/F103゜203
is set to "1", making it possible to detect a failure.

In addition, priority order F/F102.202 is used for AND gate 10 when memory access requests from each processing device occur simultaneously.
5. The outputs 113 and 213 of 205 each become "1", the halt condition of the priority F/Fs 102 and 202 is canceled, and the negative logic output 1 of the priority F/F 102.202 is newly released.
18,218 is input and set,
The priority order changes alternately each time a conflict occurs.

〔Effect of the invention〕

As described above, the present invention has the effect that in a system that exclusively manages processing requests for shared resources, it is possible to sufficiently check the contention control circuit, and the reliability of the device can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... Processing device (I), 2... Processing device (I),
3... Main memory, 101, 20 request F/F
, 102.202...Priority order F/F, 103,203
,,,Fault display F/F, 104,105,107゜1
09.204,205,207,209・,-and gate, 106,206... Nantes gate, 108.2
08...-Number construction circuit.

Claims (1)

[Claims] A failure between the processing devices in which processing requests are made from two processing devices to a shared resource, and processing request information for the shared resource is mutually sent between the processing devices, and in the event of a conflict, one of the processing requests is suppressed. In the detection method, means for mutually sending execution suppression information generated when a shared resource processing request conflicts between the respective processing devices, and means for sending execution suppression information generated within the respective processing devices to each other. A failure detection method between processing devices, comprising means for detecting whether contents of suppression information match.