JPS63228367A - Main memory access method - Google Patents

Abstract

PURPOSE:To prevent contention in a lock area access by executing the access of a specified area of a main storage device being a lock area after collating the lock control bits of other CPUs by the processes of respective CPUs executing access and checking the contention state to other CPUs. CONSTITUTION:Respective CPUs set the control bits of themselves to a logical '1', and announce that it is the access of the lock area with respect to other CPUs prior to the access of the main storage device MS. The CPUs test the lock control bits for adjusting the contention with other CPUs so as to attain synchronization. Namely, the test of the lock control bit state of other CPUs is waited until the lock control bit state of oneself is reflected with respect to all the other CPUs. When the lock control bits of other CPUs are all logical '0' (XLOCK='0') as the result of the test, the access of the storage device MS is proceeded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a main memory access method for a multiprocessor system, and in particular to a main memory access method involving lock control over a specific area on the main memory device. Technology] A multiprocessor system consisting of a main memory device and multiple processors (hereinafter referred to as CPUs) that share this main memory device, and controlled by one management program,
In general, many system resources that do not belong to any CPU,
For example, since the main storage device is shared, the system is highly flexible in resource allocation, can be expected to be highly reliable, and is economical. However, if multiple CPUs simultaneously execute a program that manages system resources, there is a possibility that the same resource will be allocated to two programs. For this reason, in a multiprocessor system, when referring to and updating (hereinafter referred to as access) various information for system management on the main memory, other CPUs cannot access the information until a series of accesses by one CPU is completed. Access should be prohibited. When a program such as an operating system manages shared resources, this access prohibition process is performed by software, for example using test-and-set instructions.

This is done using a method called software locking.

On the other hand, when a plurality of CPUs mutually use shared hardware resources in a series of hardware processes provided to a program, it is necessary to manage the shared resources as described above. for example.

When dividing the area on the main storage device into a program area that can be accessed by a program and a hardware area that cannot be accessed by a program, and sharing the hardware area among multiple CPUs, the above-mentioned access prohibition process is required. becomes.

When implementing the software locking method using the test-and-set instruction described above using a microprogram, a lock flag that can be referenced and updated by multiple CPUs is stored in a flip-flop or in a hardware area of the main memory. It is necessary to perform exclusive control of the shared area using this lock flag. According to this software method, lock control is performed as part of the access procedure, so access to areas other than the relevant shared area is permitted for any CP tJ, and the main memory can be accessed without the need for special hardware. It becomes possible to realize a partial lock function of the device.

A prior art related to this type of software-based lock management mechanism is described in, for example, Japanese Patent Laid-Open No. 164462/1983.

(Problems to be Solved by the Invention) However, in the software-based lock management mechanism of the prior art, lock flags are configured on a shared resource among multiple CPUs, and contention in lock flag updates is controlled on the flag side. It is necessary to do it.

If the lock flag is configured on the main memory, which is the most universal resource shared among multiple CPUs, no special hardware is required to implement the lock flag, but there is no need for special hardware to implement the lock flag. contention must be controlled by hardware. This is normally done by hardware locking the main memory during flag reference updates, but this hardware lock temporarily prohibits access to other areas unrelated to the locked area. However, there is an undeniable drop in performance.

On the other hand, when the lock flag is configured with a flip-flop, separate hardware connected to each of the plurality of CPUs via signal lines and a logic circuit for centrally controlling contention are required. In particular, in the case of a multiprocessor system consisting of a large number of CPUs, 48
There were problems in that the number of bins increased and the configuration and control logic became complicated.

The present invention has been made to solve the above problems.

An object of the present invention is to perform the lock control without implementing the lock flag on a shared resource between a plurality of CPUs such as a main storage device or separate hardware.

Provides a main memory access method that facilitates system configuration even when the number of CPUs configuring a multiprocessor system increases by controlling contention for lock area access on each CPU side, as each CPU tends to have a lock flag. It's about doing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief summary of one typical aspect of the present invention that has been made to achieve the above object is as follows.

In the present invention, lock flags (lock control bits) for performing lock control are distributed among each CPU, and each CPU performs lock control without updating each other's lock flags. , and contention control for access to the lock area will be performed independently on each CPU side.

That is, in a multiprocessor system consisting of N CPUs and a main memory shared by the N CPUs, a lock control bit that can be set and reset only by the own CPU and can be referenced by other CPUs is set as described above. Each CPU has a number of units (k=0, 1,
2. ....

When the CPU N-1) accesses a specific area of the main storage device, it sets the lock control bit of its own CPU to logic 111 PI, and the state of the lock control bit of its own CPU is set to 111 PI. When it is reflected on other CPUs,
i#Jc (i=0.l, 2...., ni-1, ni+
1. ..., N-1), if the logical sum of the lock control bits of N-1 other CPUs is in On, then
A specific area of the main storage device is accessed, and upon completion of the access, the lock control bit of the CPU is reset to logic 'o'''.
- The logical sum of lock control bits of one other CPU is “°1”
k-, which has a higher access priority than its own CPU, which is 1' and has a higher access priority than its own CPU, where
If the logical sum of the lock control bits of one other CPU is OII, then if
(7) When the logical sum of the lock control bits becomes '0', access the specific area of the main storage device, and at the end of the access, set the lock control bit of the own CPU to logic '0'. ″. Also, if the i≠k
The logical sum of N-1 lock control bits is lll1
k-, which has a higher re-access priority than its own CPU, where t<it (i==0, 1, 2.--, ni-1)
If the logical sum of the lock control bits of one other CPU is 1'', the lock control bit of the own CPU is reset to -carrying logic II O71, and then the own CPU
When the state of the lock control bit of the CPU is reflected in all other CPUs, the lock control bit of the CPU is set to logic "1" again, and the state of the lock control bit of the CPU is set to logic "1", and The logical sum of the CPU lock control bits is 110'g
At the point in time, the specific area of the main storage device is accessed, and upon completion of the access, the second lock control bit of the own CPU is reset to logic "0".

[Effect]

As a result, each cPU process accessing a specific area of the main memory that is a lock area can be accessed by other CPU processes.
Since this is performed after checking the contention state with other CPtJs by referring to the lock control bit of the PU, no contention occurs in accessing the lock area.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Figure 2 shows three CPUs in one embodiment of the present invention and
1 is a diagram showing the configuration of a multiprocessor system including a main memory MS shared by two CPUs.

In FIG. 2, main memory MS is divided into a program area that can be accessed by a program and a hardware area that cannot be accessed by a program. Here, three CPU0. A main memory access method involving lock control when accessing a shared area in the hardware area that can be mutually referenced and updated by the CPU1 and CPU2 will be described.

FIG. 1 is a diagram schematically showing the main parts of the hardware configuration of three CPUs configuring a multiprocessor system according to an embodiment of the present invention.

CPU0. which constitutes this multiprocessor system. C
PUI and CPU2 each have a lock control bit of 1,
2.3, and these lock control bits 1 and 2.3 are
Each CPU has a
Signal lines 101, 102, 103, 104, 105, 10
They are connected to each other at 6,107°108. Each of these C
Lock control bits 1.2.3 present in the PU are
It is a flip-flop that can be set and reset only in U, and each CPU sets its own lock control bit to logic "1" when accessing the shared area of the main memory MS.
Set to . Signal line 101 connecting each CPU
, 102, 103, and 104 are signal lines that transmit the state of the lock control bits to other CPUs having a lower priority than the own CPU, and at least one of the lock control bits of the other CPUs having a higher priority than the own CPU logic 1419
If so, then the signal line is 1". Taking CPU1 as an example, signal line 102 reflects the value of lock control bit 1 of CPU0, and line 103 reflects the logic of line 102 and lock control bit 2 of CPU1. The summed value is reflected and sent to the CPU 2. Also, the signal lines 101, 102.10 here
3 states are respectively CptJot t, 2c7)XPL
OCtl: Reflected in the test conditions.

Therefore, when XPLOCK="1", it indicates that at least one lock control bit of a CPU having a higher priority than its own CPU is logic n l 7'.

On the other hand, the signal lines 105, 106, 107, and 108 are connected to the own CPtJ in contrast to the signal lines 101, 102, 103, and 104.
This is a signal line that transmits the logical sum of the lock control bits of a CPU with a lower priority than its own CPU to a CPU with a higher access priority. The signals on signal lines 109, 110, and 111 are respectively.

Shinei101 and 107. It is a signal obtained by taking the logical sum of signal lines 102 and 106°, signal lines 103 and 105, and XLOC
This is reflected in the test condition K.

Therefore, when XLOCK="I n", at least one lock control bit of another CPU is set to logic it 1
Indicates that it is r+.

FIG. 3 is a flowchart showing a procedure for accessing the shared area when each CPU accesses the main memory MS according to an embodiment of the present invention.

Each CPU accesses the shared area.

If lock control for other CPUs is required, processing is performed according to the access procedure shown in FIG.

Next, the processing of this access procedure will be explained with reference to FIG.

Each CPtJ prior to accessing the main memory MS.

Set the lock control bit of the own CPU to logic 11177 and declare to other CPUs that the lock area is being accessed (step 100). Next, set the lock control bit of the other CPU to adjust the contention with other CPUs. Test bits and synchronize (step 200°, step 500)
. Here, to test the lock control bit state of another CPU, it is necessary to wait after setting the lock control bit of the own CPU until the state of the lock control bit of the own CPU is reflected to all other CPUs. This is to ensure that even if multiple CPtJs set their own lock control bits at the same time, the states of each other's lock control bits are always reflected in the test at the stage of performing the test, and priority order among CPUs can be maintained. be.

As a result of the above test, if all the lock control bits of the other CPUs are logic "'0'"(XLOCK="'O") (step 200), the other CPUs have locked access to the main memory MS. Since there is no memory, the process proceeds to step 300 to access the main memory MS.

Conversely, at least one of the lock control bits of other CPUs
If the logical pabi'(XLOCK="bi") (step 200), processing continues with the test (XPLO
Proceed to CK="l"). This step 5oo test is to test the state of the lock control bits of other CPUs with higher access priority by the own CPU, and as a result of the test, all the lock control bits of other CPUs with higher priority than the own CPU are logic 110H. (XPLOCK="O")
If so, the process returns to step 200 for testing.

At this time, the priority of the own CPU that declared access by setting the lock control bit to logic 111 gH is the highest, and another CPU with a lower priority is accessing the main memory MS, Step 200. The test in step 500 is repeated and waits for the access right to be released upon completion of the access to the main memory MS by another CPU with a lower priority that is currently accessing the main memory MS. Among the lock control bits of other CPUs that have higher access priority than the own CPU.

At least one is logic “1” (XPLOCK=”BI’)
If so, processing proceeds to step 600. Step 60
0, the lock control bit of the own CPU is reset to logic "0'', releasing the access declaration of the main memory MS to other CPUs, and the state of the lock control bit of the own CPU is After waiting a predetermined time for it to be reflected on the current CPU, the process returns to step 100 and the current CPU
Set the lock control bit of PtJ to logic bit ', and
It declares to the PU that it is a lock area access and performs lock control processing. In this way, other C
Coordinates access contention with the PU.

Furthermore, after the access to the main memory MS is finally completed, in the process of step 400, the lock control bit of the own CPtJ is reset to logic "0", thereby granting access rights to the main memory MS to other CPUs. Release and exit the lock control processing state.

In this embodiment, the case where there are three CPUs is described, but in the present invention, each CPU has a lock control bit,
Furthermore, since the lock control logic is processed independently by each CPU, it will be easily understood that the same implementation is possible even when there are three or more CPUs.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of CPUs
Lock control can be easily implemented without requiring hardware that implements lock flags shared between devices. In addition, each CPU has a lock control bit that can be set and reset only by its own CPU, and this lock control can be performed by the lock control logic of only its own CPU, and the lock control logic is distributed among each CPU. is common, so
A multiprocessor system can be easily configured by simply combining multiple CPUs of the same type.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram schematically showing the main parts of the hardware configuration of three CPUs constituting a multiprocessor system according to an embodiment of the present invention, and FIG. With 3 CPUs. FIG. 3 is a block diagram showing the configuration of a multiprocessor system consisting of a main memory MS shared by three CPUs. FIG. be. In the figure, l, 2.3...Lock control bit, 4-12.
...OR gate, 101-110...Signal line. Agent: Patent attorney Katsuma Ogawa, -1L,)゛・,-1

Claims (1)

[Claims] 1. In a multiprocessor system consisting of N processing units and a main memory shared by the N processing units, an identifier that can be set and reset only by the own processing unit and that can be referenced by other processing units is provided. The k-th (k=0, 1, 2, . . .
. . , N-1) when accessing a specific area of the main storage device, the
When the th identifier is set to logic "1" and the state of the identifier of the own processing device is reflected in all other processing devices, i≠
k (i=0, 1, 2,..., k-1, k+1...,
If the logical sum of the identifiers of N-1 other processing devices (N-1) is "0", the specified area of the main storage device is accessed, and upon completion of the access, the k-th processing device of the own processing device is accessed. the i≠k
The logical sum of the identifiers of N-1 other processing devices is “1”
and i<k (i=0, 1, 2, ..., k-1), and the logical sum of the identifiers of k-1 other processing devices that have higher access priority than the own processing device is "0" , the above i
The logical sum of the identifiers of N-1 other processing devices where ≠k is “
0'', the specific area of the main storage device is accessed, and upon completion of the access, the k-th identifier of the own processing device is reset to logical ``0'', and the N-1 where i≠k is The logical sum of these identifiers is “1” and 1<k(1
= 0, 1, 2, ..., k-1) If the logical sum of the identifiers of k-1 other processing devices that have higher access priority than the own processing device is "1", the self-processing After resetting the k-th identifier of the device to one-way logic "0", when the state of the identifier of the own processing device is reflected in all other processing devices, the k-th identifier of the own processing device is reset again. The logic “1”
”, and when the logical sum of the identifiers of N-1 other processing devices where i≠k becomes “0”, the specific area of the main storage device is accessed, and when the access is completed, the own processing A main memory access method characterized in that the k-th identifier of the device is reset to logic "0".