JPH0425020A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a conductive base material installed under a contact hole from being affected at the time of patterning of an interconnection even if there is the deviation in positions between the contact hole and the interconnection by including a process in which an aluminum or aluminum alloy film is formed on an insulated film including the interior of the contact hole and a process in which the interconnection passing on the contact hole is patterned by a dry-etching device. CONSTITUTION:On a PSG insulated film 4 including the interior of a contact hole 5, an Al (alloy ircluded) film is formed in the thickness of about 500OAngstrom by a sputtering method, etc. Then, a resist pattern 9 having the width of 0.8mum which is same with the diameter of the contact hole is formed on the Al (or Al alloy) film. At the time of patterning of the Al interconnection 10, an impurity diffusion area 2 formed under the contact hole 5 which has no etch selectivity with Al is not etched even if there is the deviation in positions between the resist pattern 9 and the contact hole 5.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, especially a method for forming a contact hole, even when a positional shift occurs between the contact hole and the wiring, the lower part of the contact hole is removed during patterning of the wiring. By providing a method for forming a contact hole that does not erode the conductive substrate, we aim to improve the degree of integration by eliminating the land portion formed on the wiring in the second part of the contact hole. a step of sequentially forming a silicon nitride film and an insulating film on a substrate; a step of forming a contact hole in the insulating film to expose the underlying silicon nitride film; and a step of forming a silicon nitride film on the exposed surface of the silicon nitride film in the contact hole. forming an integrated high melting point metal film on the insulating film, and reacting the high melting point metal and silicon nitride by heat treatment, selectively directly applying the conductive substrate surface to the bottom of the contact hole. A step of forming a covering mixed layer of high melting point metal nitride and silicon, a step of removing the remaining high melting point metal film by wet etching means, and a step of oxidizing the upper surface of the mixed layer of high melting point metal nitride and silicon. a step of forming an aluminum or aluminum alloy film on the insulating film including the inside of the contact hole; and a step of patterning the aluminum or aluminum alloy film into a wiring shape passing over the contact hole by dry etching means. Configure.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a contact hole.

As the integration of VLSI and other devices progresses, the width of aluminum (including aluminum alloy) wiring and the diameter of contact holes are becoming smaller. They tend to be the same size.

However, in this case, if a misalignment occurs between the contact hole and the AA wiring when patterning the Al film into a wiring shape, the conductive substrate, such as silicon (Si), will be exposed at the bottom of the contact hole during etching during patterning. Problems arise in that the substrate is etched and the pn junction formed thereon is destroyed.

Therefore, a process is desired in which the conductive substrate under the contact hole is not eroded even if the contact hole and the wiring are misaligned.

[Conventional technology]

FIGS. 3(a), 3(b), and 3(C) are diagrams schematically showing conventional techniques for forming wiring.

In conventional technology, silicon dioxide (
Using a silicate glass insulating film such as SiO□ or phosphosilicate glass (PSG), the silicate glass insulating film is directly deposited on a conductive substrate, such as a Si substrate, and a contact hole is formed in it to expose the surface of the Si substrate. By forming an Al film on the insulating film including the inside of the contact hole, and patterning this Al film into a wiring shape, an AA wiring led out from the Si substrate onto the insulating film was formed.

When using such conventional technology to form a highly integrated semiconductor device with the same wiring width and contact hole diameter, the third
As shown in Figure (a), a contact hole 53 exposing the surface of the Si substrate 51 and an A
When the alignment with the j2 wiring 54 is done accurately,
Since the entire surface of the Si substrate 51 exposed in the contact hole 53 is covered with the beta wiring 54 having a resist film on top, the 14' film that is etched away when patterning the An wiring 54 is entirely A1. Since the insulating film 52- has etching selectivity, no problem occurs.

However, as shown in FIG. 3(b), there is a positional deviation between the contact hole 53 and the Al wiring 54 (currently ±0.
2 μm), from the part of the AA wiring 54 whose upper part is covered with the resist to the part of the AA wiring 54 which is not covered with the resist.
j? The contact hole 53 protrudes from the area where the film is etched away, and due to over-etching after the Aj7 film other than the wiring area has been removed, etching has selectivity with respect to the Aβ exposed within the contact hole 53. The unetched surface of the Si substrate 51 is etched, and this Si substrate 5
A problem arises in that the pn junction formed in 1 is destroyed.

Therefore, as shown in FIG. 3(C), in the past, even when a positional shift occurs between the contact hole 53 and the Al wiring 54, the contact hole 53 is prevented from protruding into the area where the l film is removed. , the contact hole 5 of the Al wiring 54
For example, set the width at the top of 3 to 0.4 μm on each side.
The land portion 55 which has been enlarged to a certain extent is provided to prevent the above problem from occurring.

[Problem to be solved by the invention]

However, in the conventional technology in which the land portion 55 is provided in a region corresponding to the second portion of the contact hole 53 of the AA wiring 54, the wide width occupied by the land portion 55 hinders high integration of the semiconductor device. There was a problem with being exposed.

SUMMARY OF THE INVENTION Therefore, the present invention provides a method for forming a contact hole in which the conductive substrate under the contact hole is not attacked during patterning of the wiring even when a positional shift occurs between the contact hole and the wiring. The purpose is to improve the degree of integration by eliminating the runt part formed on the upper wiring.

[Means to solve the problem]

The two-part task involved forming a silicon nitride film and an insulating film sequentially on a conductive substrate, forming a contact hole in the insulating film to expose the underlying silicon nitride film, and forming a contact hole in the insulating film to expose the underlying silicon nitride film. forming a refractory metal film integral with the insulating film including the exposed surface of the silicon nitride film;
Heat treatment causes high melting point metal and silicon nitride to react,
A step of selectively forming a mixed layer of high melting point metal nitride and silicon directly covering the surface of the conductive substrate at the bottom of the contact hole, and a step of removing the remaining high melting point metal film by wet etching means. a step of oxidizing the upper surface of the mixed layer of high melting point metal nitride and silicon; and a step of forming an aluminum or aluminum alloy film on the insulating film including the inside of the contact hole.
This problem is solved by the method of manufacturing a semiconductor device according to the present invention, which includes the step of patterning the aluminum or aluminum alloy film into a wiring shape that passes over the contact hole using a dowel etching method.

[For production]

That is, in the method of the present invention, a silicon nitride film is formed in advance under a silicate glass insulating film, this silicon nitride film is exposed at the bottom of a contact hole, and the exposed silicon nitride film and titanium film are bonded together. A mixed layer of titanium nitride (TiN) and Si (TiN/Si layer) is selectively formed only at the bottom of the contact hole, and this Ti
After oxidizing the upper surface of the N/Si layer and forming an oxide film thereon that has etching selectivity with Al, an AA layer is formed on the contact hole, and this Al layer is patterned into the wiring shape by dry etching. I do. Therefore, A
When patterning the l film, contact holes and Aj
Even if misalignment with the two wirings occurs, the oxide film on the TiN/Si layer serves as an etching mask, and the surface of the Si substrate below the contact hole, for example, is not attacked.

Therefore, in order to cover the misalignment between the contact hole and the AA wiring, the second part of the contact hole is
- There is no need to form a wide land portion, and the degree of integration can be improved accordingly.

Separately, the TiN/Si layer and its oxide film are Al and S.
Since it acts as a diffusion barrier for i, it also has the effect of preventing junction breakdown at the bottom of the contact hole.

Note that it has been confirmed that contact resistance does not increase due to the presence of the TiN/Si layer and its oxide film.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIGS. 1(a) to (g) are process cross-sectional views of one example of connecting wiring to a semiconductor substrate, and FIGS. 2(a) to (d) are process cross-sectional views of another example of connecting wiring between layers. It is a process sectional view of an example.

Identical objects are indicated by the same reference numerals throughout the figures.

Refer to FIG. 1(a) When forming the A1 (including AA gold alloy) wiring drawn out onto the insulating film from the impurity diffusion region 2 formed on the Si substrate I by the method of the present invention, the impurity diffusion region 2 is On the formed Si substrate I, first, a silicon nitride (Si3N4) film 3 with a thickness of 500A is formed by the usual CVD method,
Next, the second step is to reduce the thickness to about 5,000 layers using the CVD method.
A phosphosilicate glass (PSG) film 4 is formed.

Refer to FIG. 1(b) Next, the PSG film 4 above the impurity diffusion region 2 is coated with the lower 513N4 film 3 by ordinary photolithography.
A contact hole 5 with a diameter of, for example, about 0.8 μm is formed to expose the.

Refer to FIG. 1 FC+.
An integral titanium (Ti) film 6 having a thickness of about 200 Å is formed on the PSG film 4'' including the exposed surface by sputtering.

Refer to FIG. 1(d) Next, this substrate is annealed at a temperature of about 500°C in a vacuum of about 10-' Torr to selectively remove the Si3N4 film 3 exposed at the bottom of the contact hole 5. , the bottom part is completely reacted with Ti, and titanium nitride (
A mixed layer 7 of TiN)/Si is formed.

Refer to FIG. 1 (fe) Next, only the Ti film 6 remaining on the surface of the substrate is selectively removed by wet etching using hydrofluoric acid or the like.

Refer to Figure 1) Next, this substrate is annealed for a desired time at a temperature of about 450° C. in a vacuum or nitrogen having a partial pressure of oxygen of about 1 to 10 Torr, and the contact hole 5 is
An oxide film 8 with a thickness of about 100 m is formed on the upper surface of the inner TiN/Si mixed layer 7.

Refer to FIG. 1(g) Next, the PSGS including the inside of the contact hole 5 is
A film (including alloy) with a thickness of about 5,000 layers is formed on the rim film 4 by sputtering or the like, and secondly,
A resist pattern 9 passing through the upper part of the contact hole diameter and having a width of 0.8 μm, which is equivalent to the contact hole diameter, is formed by a photo process, and this resist pattern 9
Using this as a mask, patterning is performed by reactive ion etching using a chlorine (CI) gas such as CCl4.5iC14 and BCl3 to form an AA (including alloy) wiring IO.

When patterning this Aj2 wiring 10, even if there is a positional shift between the resist pattern 9 and the contact hole 5 as shown in the figure, the Aj2 wiring 10 may be exposed outside the resist pattern 9.
After the A2 film is removed, at the bottom of the contact hole 9,
TiN/Si? Since the oxide film 8 on the Ji4 composite layer 7 is exposed and acts as an etching barrier, the impurity diffusion region 2 under the contact hole 9, which has no etching selectivity with AA, is not etched, and the p - Destruction of the n-junction is prevented.

In this method, the TiN/Si mixed layer 7 and the oxide film 8 on its surface are interposed between the impurity diffusion region 2 and the AA wiring 10, but it has been confirmed that this does not cause an increase in contact resistance. There is.

Next, an example of interconnection between wiring layers will be described with reference to FIGS. 2(a) to 2(d).

Referring to FIG. 2(a), a lower layer of, for example, tungsten (W) is deposited on the lower insulating film 11! Using a substrate to be processed on which A12 has been formed, sLI with a thickness of about 500A is first deposited on the surface by CVD method.
A J4 film 3 is formed, and a PSG film 4, which is a 0A insulating film, is formed to a thickness of about 5,000, for example, on the second layer, and a contact hole is formed on the W wiring I2 by lithography to expose the upper surface of the 5i3N4 film 3. form 5.

FIG. 2 (see BL) Next, a Ti film 6 with a thickness of about 2QOA is formed on this substrate, and contact holes 5 are formed by heat treatment similar to the previous embodiment.
A TiN/Si mixed layer 7 covering the W wiring 12 is selectively formed at the bottom.

Refer to FIG. 2(C) Next, after removing the remaining Ti film 6 by wet etching, the upper surface of the TiN/Si mixed layer 7 is formed to a thickness of 100 mm by heat treatment in an oxygen-containing atmosphere similar to the previous embodiment.
An oxide film 8 of approximately A is formed.

Referring to FIG. 2(d), the AA wiring 10 passing above the contact hole 5 is formed on the PSG film 4 by the same method as in the previous embodiment.

In this case as well, even if there is a misalignment between the contact hole 5 and the AA wiring 10 as shown in the figure, the oxide film 8 of the TiN/Si mixed layer 7 exposed in the contact hole 5 allows the AA
The W wiring 12, which does not have selectivity, is protected by etching during film patterning.

Note that, as in the previous embodiment, the contact resistance does not increase due to the presence of the TiN/5il1 composite layer 7 and its oxide film 8.

〔Effect of the invention〕

As described above, according to the method of the present invention, even if the contact hole and the wiring are misaligned and the contact hole protrudes outside the Al wiring pattern, the lower part of the contact hole can be removed by etching during patterning of the AI2 wiring. The Si substrate or underlying wiring will not be attacked.

Therefore, it is not necessary to provide a wide land portion on the wiring in the second part of the contact hole in order to cover the above-mentioned positional deviation, and the semiconductor device can be highly integrated.

[Brief explanation of the drawing]

1(a) to (g) are process sectional views of one embodiment of the method of the present invention; FIGS. 2(a) to (d) are process sectional views of another embodiment of the method of the present invention; Figures 3 (a) and (b) are as follows. (C) is a schematic diagram of the conventional technology, 1 is a Si substrate, 2 is an impurity diffusion region, 3 is a 313N4 film, 4 is a PSG film, 5 is a contact hole, 6 is a Ti film, 7 is a TiN/Si mixed layer , 8 is an oxide film, 9 is a resist pattern, 10 is an AA wiring, 11 is a lower layer insulating film, and 12 is a lower layer W wiring.

Claims (1)

[Scope of Claims] A step of sequentially forming a silicon nitride film and an insulating film on a conductive substrate; a step of forming a contact hole in the insulating film to expose the underlying silicon nitride film; forming an integrated refractory metal film on the insulating film including the exposed surface of the silicon nitride film; reacting the refractory metal and silicon nitride through heat treatment;
selectively forming a mixed layer of high melting point metal nitride and silicon directly covering the surface of the conductive substrate at the bottom of the contact hole; and removing the remaining high melting point metal film by wet etching. oxidizing the upper surface of the mixed layer of high melting point metal nitride and silicon; forming an aluminum or aluminum alloy film on the insulating film including the inside of the contact hole; and the aluminum or aluminum alloy film. 1. A method of manufacturing a semiconductor device, comprising the step of patterning the contact hole into a wiring shape passing over the contact hole by dry etching means.