JPH04251996A - Method for mounting semiconductor components - Google Patents

Method for mounting semiconductor components

Info

Publication number
JPH04251996A
JPH04251996A JP3001299A JP129991A JPH04251996A JP H04251996 A JPH04251996 A JP H04251996A JP 3001299 A JP3001299 A JP 3001299A JP 129991 A JP129991 A JP 129991A JP H04251996 A JPH04251996 A JP H04251996A
Authority
JP
Japan
Prior art keywords
circuit board
solder
leads
lead
semiconductor component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3001299A
Other languages
Japanese (ja)
Inventor
Kimio Hosoya
細谷　喜美夫
Mamoru Shinjo
新城　護
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3001299A priority Critical patent/JPH04251996A/en
Publication of JPH04251996A publication Critical patent/JPH04251996A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To provide at a low cost a method for mounting semiconductor components on the surface of a circuit board applicable to a circuit board apparatus of multikind low-production. CONSTITUTION:Solder layers 15 are formed in desired thicknesses on the setting surfaces 11A of leads 11 of a semiconductor component 10 and then using the solder layers 15 the leads 11 are joined to the board 1 by a reflow soldering thereby the mount the semiconductor component 10 on the surface of the circuit board 1.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は、半導体部品を回路基板
に表面実装する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for surface mounting semiconductor components on a circuit board.

【０００２】0002

【従来の技術】図４の（Ａ），（Ｂ）　は従来方法の工
程を示す図である。半導体部品１０を回路基板１に表面
実装する為に、回路基板１の実装面には、リード１１の
着座面１１Ａ　に対応して、パッド２を配列形成してあ
る。2. Description of the Related Art FIGS. 4A and 4B are diagrams showing the steps of a conventional method. In order to surface-mount the semiconductor component 10 on the circuit board 1, pads 2 are formed in an array on the mounting surface of the circuit board 1, corresponding to the seating surface 11A of the lead 11.

【０００３】従来は図４の（Ａ）　に図示したように、
まず回路基板１の実装面に配列したパッド２上にクリー
ム状半田５をスクリーン印刷して形成する。その後、図
４の（Ｂ）　に図示したようにリード１１を対応するパ
ッド２に位置合わせして、半導体部品１０を回路基板１
に載せ、加熱しリフロー半田付けすることで、回路基板
１に半導体部品１０を表面実装している。Conventionally, as shown in FIG. 4(A),
First, creamy solder 5 is formed by screen printing on the pads 2 arranged on the mounting surface of the circuit board 1. Thereafter, as shown in FIG. 4B, the leads 11 are aligned with the corresponding pads 2, and the semiconductor component 10 is placed on the circuit board 1.
The semiconductor component 10 is surface-mounted on the circuit board 1 by placing the semiconductor component 10 on the circuit board 1, heating it, and performing reflow soldering.

【０００４】なお、この半導体部品１０はＱＦＰ（ｑｕ
ａｄｅ　ｆｌａｔｐａｃｋａｇｅ）型の半導体部品であ
って、帯状の金属材をプレス加工して、それぞれの短冊
形のフレーム枠素子の内側縁から、多数のリードが内側
に突出して配列した枠形のリードフレームを設け、それ
ぞれのリードの着座面側の先端をそれぞれのフレーム枠
素子に連結し接続させる。Note that this semiconductor component 10 is a QFP (qu
It is a frame-shaped lead frame in which a strip-shaped metal material is pressed and a large number of leads are arranged and protrude inward from the inner edge of each rectangular frame element. and the ends of the respective leads on the seating surface side are connected to the respective frame elements.

【０００５】次にそれぞれのリードをほぼＺ形に成形し
、その状態で半導体チップとリードとを一体にパッケー
ジングし、最後にフレーム枠素子に繋がっている着座面
の先端部を切断して、それぞれのリードを分離したもの
である。[0005] Next, each lead is formed into a substantially Z-shape, the semiconductor chip and the leads are packaged together in this state, and finally, the tip of the seating surface connected to the frame element is cut off. Each lead is separated.

【０００６】[0006]

【発明が解決しようとする課題】ところで、スクリーン
印刷時に用いるメタルマスクは、ホトリソグラフィ手段
によりパターン孔を穿孔しているので、メタルマスクの
製造工数が多いこと、及びパッドの配列が異なる毎にメ
タルマスクを製作しなければならないということの２つ
理由により、スクリーン印刷法による従来の半導体部品
の実装方法は、多種少量生産の回路基板装置に適用して
コスト高になるという問題点があった。[Problems to be Solved by the Invention] Incidentally, in the metal mask used in screen printing, pattern holes are perforated by photolithography means, so the number of man-hours required for manufacturing the metal mask is large, and the number of metal Due to the two reasons that masks must be manufactured, the conventional mounting method of semiconductor components using the screen printing method has the problem of high costs when applied to circuit board devices that are produced in a wide variety of small quantities.

【０００７】本発明はこのような点に鑑みて創作された
もので、多種少量生産の回路基板装置に適用して、低コ
ストの半導体部品の実装方法を提供することを目的とし
ている。The present invention was created in view of the above points, and an object of the present invention is to provide a low-cost mounting method for semiconductor components that can be applied to circuit board devices that are produced in a wide variety of small quantities.

【０００８】[0008]

【課題を解決するための手段】上記の目的を達成するた
めに本発明は、図１に示したように、半導体部品１０の
リード１１の着座面１１Ａ　に、所望厚の半田層１５を
形成し、その半田層１５を用いてリード１１をリフロー
半田付けして、回路基板１に半導体部品１０を表面実装
する構成とする。[Means for Solving the Problems] In order to achieve the above object, the present invention, as shown in FIG. 1, forms a solder layer 15 of a desired thickness on the seating surface 11A of the lead 11 of the semiconductor component 10. The semiconductor component 10 is surface-mounted on the circuit board 1 by reflow soldering the leads 11 using the solder layer 15.

【０００９】半田層を形成する手段としては、図２に例
示したように、リード１１がリードフレーム２０に配列
した状態で、それぞれの着座面１１Ａ　に半田箔２５を
貼着する。 或いはまた，図３に例示したように、リード１１がリー
ドフレーム２０に配列した状態で、それぞれの着座面１
１Ａ　に半田めっき層３５を形成する。As a means for forming the solder layer, as illustrated in FIG. 2, with the leads 11 arranged on the lead frame 20, solder foil 25 is attached to each seating surface 11A. Alternatively, as illustrated in FIG. 3, with the leads 11 arranged on the lead frame 20, each seating surface 1
1A, a solder plating layer 35 is formed.

【００１０】0010

【作用】本発明方法によれば、メタルマスクを製作する
必要がない。したがって、多種少量生産の回路基板装置
に適用して、低コストである。[Operation] According to the method of the present invention, there is no need to manufacture a metal mask. Therefore, it can be applied to circuit board devices produced in a wide variety of small quantities at low cost.

【００１１】[0011]

【実施例】図１の（Ａ），（Ｂ）　は本発明方法の工程
を示す図、図２の（Ａ），（Ｂ），（Ｃ）　は本発明の
実施例の工程を示す図、図３の（Ａ），（Ｂ）　は本発
明の他の実施例の工程を示す図である。[Example] Figures 1 (A) and (B) are diagrams showing the steps of the method of the present invention, and Figures 2 (A), (B), and (C) are diagrams showing the steps of the example of the present invention. FIGS. 3A and 3B are diagrams showing the steps of another embodiment of the present invention.

【００１２】図１において、半導体部品１０を回路基板
１に表面実装する為に、回路基板１の実装面には、リー
ド１１の着座面１１Ａ　に対応して、パッド２を配列形
成してある。なお、溶融半田槽に回路基板をディップす
ることで、他の回路部品用のパッドに薄い半田層を形成
する際に同時に、半導体部品１０を表面実装する上記の
パッド２の表面にも、薄い（５μｍ　程度）半田層が形
成されている。In FIG. 1, in order to surface-mount a semiconductor component 10 on a circuit board 1, pads 2 are arranged and formed on the mounting surface of the circuit board 1 in correspondence with the seating surface 11A of the lead 11. Note that by dipping the circuit board in a molten solder bath, when forming a thin solder layer on pads for other circuit components, a thin ( A solder layer (approximately 5 μm) is formed.

【００１３】一方、図１の（Ａ）　に図示したように、
半導体部品１０のそれぞれのリード１１の着座面１１Ａ
　には、所望の層厚（５０μｍ　〜　１５０μｍ　）の
半田層１５を形成する。その後、図１の（Ｂ）　に図示
したように、リード１１を対応するパッド２に位置合わ
せして、半導体部品１０を回路基板１に載せ、加熱し半
田層１５を半田リフローさせてリード１１をパッド２に
半田付けして、半導体部品１０を回路基板１に表面実装
する。On the other hand, as shown in FIG. 1(A),
Seating surface 11A of each lead 11 of semiconductor component 10
Then, a solder layer 15 having a desired layer thickness (50 μm to 150 μm) is formed. Thereafter, as shown in FIG. 1B, the leads 11 are aligned with the corresponding pads 2, the semiconductor component 10 is placed on the circuit board 1, and the leads 11 are heated to reflow the solder layer 15. The semiconductor component 10 is surface mounted on the circuit board 1 by soldering to the pad 2.

【００１４】図２において、２０は帯状の金属材をプレ
ス加工して、それぞれの短冊形のフレーム枠素子の内側
縁から、多数のリード１１を内側に突出して配列させた
枠形のリードフレームであって、それぞれのリード１１
の着座面１１Ａ　側の先端は、それぞれのフレーム枠素
子に繋がっている。In FIG. 2, reference numeral 20 denotes a frame-shaped lead frame in which a large number of leads 11 are arranged and protruded inward from the inner edge of each rectangular frame element by pressing a band-shaped metal material. There, each lead 11
The ends on the seating surface 11A side are connected to the respective frame elements.

【００１５】そして、リード１１が平面状に配列した状
態で、図２の（Ａ）　に図示したように、着座面１１Ａ
　に導電性接着剤２１を塗布する。次に図２の（Ｂ）　
に図示したように細長い短冊形の半田シート２５０（厚
さは例えば１００　μｍ　程度）　を着座面１１Ａ　に
架橋させ、導電性接着剤２１により半田シート２５０を
着座面１１Ａ　に貼着させる。　　なお、導電性接着剤
２１をリード１１側に塗布することなく、半田シート２
５０　の片面にまず導電性接着剤２１を塗布し、その後
半田シート２５０　をリード１１側に貼着するようにし
ても良い。Then, with the leads 11 arranged in a plane, as shown in FIG. 2A, the seating surface 11A is
A conductive adhesive 21 is applied to the surface. Next, (B) in Figure 2
As shown in the figure, an elongated rectangular solder sheet 250 (thickness, for example, about 100 μm) is bridged onto the seating surface 11A, and the solder sheet 250 is adhered to the seating surface 11A with a conductive adhesive 21. Note that the solder sheet 2 is not coated with the conductive adhesive 21 on the lead 11 side.
The conductive adhesive 21 may be first applied to one side of the lead 11, and then the solder sheet 250 may be attached to the lead 11 side.

【００１６】そしてナイフ等を用いて、リード間の不用
の半田シートを切り落として、リード１１の着座面１１
Ａ　に半田箔２５を残す。その後、リード１１をほぼＺ
形にプレス加工し、その状態で半導体チップとリードと
を一体にパッケージングし、最後にフレーム枠素子に繋
がっている着座面の先端部を切断して、図２の（Ｃ）　
に図示したようにそれぞれのリードを分離する。Then, using a knife or the like, cut off the unnecessary solder sheet between the leads and seal the seating surface 11 of the lead 11.
Leave solder foil 25 on A. After that, lead 11 is almost Z
The semiconductor chip and leads are packaged together in that state, and finally the tip of the seating surface connected to the frame element is cut off, as shown in Figure 2 (C).
Separate each lead as shown in the diagram.

【００１７】その後、リード１１を対応するパッドに位
置合わせして、半導体部品１０を回路基板に載せ、加熱
し半田箔２５をリフロー用半田として、リード１１をパ
ッド２に半田付けする。Thereafter, the leads 11 are aligned with the corresponding pads, the semiconductor component 10 is placed on the circuit board, and the leads 11 are soldered to the pads 2 by heating and using the solder foil 25 as reflow solder.

【００１８】図３に示す手段は、リード１１が平面状に
リードフレーム２０に配列した状態で、リード１１の着
座面１１Ａ　を除いたリードフレーム２０の全面を、ポ
リエステル系等のマスキングテープで覆い、半田めっき
して図３の（Ａ）　に図示したように、着座面１１Ａ　
に所望の厚さの半田めっき層３５を形成する。The means shown in FIG. 3 covers the entire surface of the lead frame 20 except for the seating surface 11A of the leads 11 with a masking tape made of polyester or the like, with the leads 11 arranged in a plane on the lead frame 20. The seating surface 11A is plated with solder as shown in Fig. 3(A).
A solder plating layer 35 of a desired thickness is formed.

【００１９】その後、リード１１をほぼＺ形にプレス加
工し、その状態で半導体チップとリードとを一体にパッ
ケージングし、最後にフレーム枠素子に繋がっている着
座面の先端部を切断して、図３の（Ｂ）　に図示したよ
うにそれぞれのリードを分離する。Thereafter, the leads 11 are pressed into a substantially Z-shape, the semiconductor chip and the leads are packaged together in this state, and finally the tip of the seating surface connected to the frame element is cut off. Separate each lead as shown in FIG. 3B.

【００２０】その後、リード１１を対応するパッドに位
置合わせして、半導体部品１０を回路基板に載せ、加熱
し半田めっき層３５をリフロー用半田として、リード１
１をパッド２に半田付けする。After that, the leads 11 are aligned with the corresponding pads, the semiconductor component 10 is placed on the circuit board, and the solder plating layer 35 is heated to serve as reflow solder, and the leads 11 are aligned with the corresponding pads.
Solder 1 to pad 2.

【００２１】[0021]

【発明の効果】以上説明したように本発明方法は、半導
体部品のリード側に半田層を設け、リフロー半田付けす
るようにしたことにより、従来のようにスクリーン印刷
用のメタルマスクを製作する必要がなくなり、多種少量
生産の回路基板装置に適用して、低コストであるという
効果がある。[Effects of the Invention] As explained above, the method of the present invention provides a solder layer on the lead side of a semiconductor component and performs reflow soldering, so there is no need to manufacture a metal mask for screen printing as in the conventional method. The present invention has the advantage that it can be applied to circuit board devices produced in a wide variety of small quantities at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】　　（Ａ），（Ｂ）　は本発明方法の工程を示
す図[Figure 1] (A) and (B) are diagrams showing the steps of the method of the present invention

【図２】　　（Ａ），（Ｂ），（Ｃ）　は本発明の
実施例の工程を示す図[Figure 2] (A), (B), and (C) are diagrams showing the steps of the embodiment of the present invention.

【図３】　　（Ａ），（Ｂ）　は本発明の他の実施例の
工程を示す図[Figure 3] (A) and (B) are diagrams showing the steps of another embodiment of the present invention.

【図４】　　（Ａ），（Ｂ）　は従来の工程を示す図[Figure 4] (A) and (B) are diagrams showing the conventional process

【符号の説明】[Explanation of symbols]

１　　回路基板、　　　　　　　　　　　　　　２　　
パッド、　　　　　　　　　　５　　クリーム状半田、
１０　　半導体部品、　　　　　　　　　　　　１１　
　リード、　　　　　　　　　　１１Ａ　着座面、１５
　　半田層、　　　　　　　　　　　　　　　　２０　
　リードフレーム、　　２１　　導電性接着剤、２５　
　半田箔、　　　　　　　　　　　　　　　　２５０　
半田シート、　　　　　　３５　　半田めっき層、1 circuit board, 2
pad, 5 creamy solder,
10 semiconductor parts, 11
Lead, 11A Seating surface, 15
solder layer, 20
Lead frame, 21 Conductive adhesive, 25
Solder foil, 250
solder sheet, 35 solder plating layer,

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】　　半導体部品（１０）のリード（１１）
の着座面（１１Ａ）　に、所望厚の半田層（１５）を形
成し、該半田層（１５）を用いて該リード（１１）をリ
フロー半田付けして、回路基板（１）　に該半導体部品
（１０）を表面実装することを特徴とする半導体部品の
実装方法。[Claim 1] Lead (11) of semiconductor component (10)
A solder layer (15) of a desired thickness is formed on the seating surface (11A) of the circuit board (1), and the leads (11) are reflow soldered using the solder layer (15) to attach the semiconductor component to the circuit board (1). (10) A method for mounting semiconductor components, comprising surface mounting. 【請求項２】　　請求項１に記載の半田層が、リード（
１１）がリードフレーム（２０）に配列した状態で、そ
れぞれの着座面（１１Ａ）　に貼着された半田箔（２５
）であること特徴とする半導体部品の実装方法。2. The solder layer according to claim 1 has a lead (
11) are arranged on the lead frame (20), the solder foils (25
) A method for mounting semiconductor components characterized by: 【請求項３】　　請求項１に記載の半田層が、リード（
１１）がリードフレーム（２０）に配列した状態で、そ
れぞれの着座面（１１Ａ）　にめっきされた半田めっき
層（３５）であること特徴とする半導体部品の実装方法
。3. The solder layer according to claim 1 has a lead (
11) is a solder plating layer (35) plated on each seating surface (11A) while arranged on a lead frame (20).
JP3001299A 1991-01-10 1991-01-10 Method for mounting semiconductor components Withdrawn JPH04251996A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3001299A JPH04251996A (en) 1991-01-10 1991-01-10 Method for mounting semiconductor components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3001299A JPH04251996A (en) 1991-01-10 1991-01-10 Method for mounting semiconductor components

Publications (1)

Publication Number Publication Date
JPH04251996A true JPH04251996A (en) 1992-09-08

Family

ID=11497596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3001299A Withdrawn JPH04251996A (en) 1991-01-10 1991-01-10 Method for mounting semiconductor components

Country Status (1)

Country Link
JP (1) JPH04251996A (en)

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Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19980514