JPH04255252A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04255252A JPH04255252A JP1614691A JP1614691A JPH04255252A JP H04255252 A JPH04255252 A JP H04255252A JP 1614691 A JP1614691 A JP 1614691A JP 1614691 A JP1614691 A JP 1614691A JP H04255252 A JPH04255252 A JP H04255252A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bonding pad
- substrate
- polyimide film
- cover insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
係り,特にチップ上に被覆されたカバー絶縁膜上に保護
膜を形成する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a protective film on a cover insulating film coated on a chip.
【0002】近年,チップ表面の保護と耐湿性の改善に
より半導体装置の信頼性を向上するため,従来のカバー
絶縁膜の上に保護膜としてポリイミド膜を被覆すること
が必要となってきている。In recent years, in order to improve the reliability of semiconductor devices by protecting the chip surface and improving moisture resistance, it has become necessary to cover the conventional cover insulating film with a polyimide film as a protective film.
【0003】本発明はこの必要性に対応し,特にボンデ
ィングパッド部において安定した保護膜の形成に利用で
きる。The present invention meets this need and can be used to form a stable protective film, particularly in bonding pad areas.
【0004】0004
【従来の技術】従来例では,アルミニウム(Al)配線
が2層のものと3層のものではボンディングパッド部の
ポリイミドの膜厚の差は 1.5〜2μm程度もあり,
パッドを露出させるためにポリイミド膜を溶解させよう
とすると, 同一溶解時間では溶解できなかった。[Prior Art] In conventional examples, the difference in the thickness of the polyimide film at the bonding pad portion between two-layer aluminum (Al) wiring and three-layer aluminum wiring is about 1.5 to 2 μm.
When trying to dissolve the polyimide film to expose the pad, it was not possible to dissolve it within the same dissolution time.
【0005】また,同一ウエハ内でもスクライブライン
上ではボンディングパッド上よりもポリイミド膜は2μ
m程度厚く被着し,ボンディングパッド上のポリイミド
膜を正規の寸法に溶解除去した場合に,スクライブライ
ン上には厚さ2μmのポリイミド膜が残ることになる。Furthermore, even within the same wafer, the polyimide film is 2 μm thicker on the scribe line than on the bonding pad.
When the polyimide film on the bonding pad is melted and removed to a regular size, a polyimide film with a thickness of 2 μm remains on the scribe line.
【0006】また逆に,スクライブライン上のポリイミ
ド膜を全部溶解しようとすると,ボンディングパッド上
の開口寸法は約2μm大きくなり,形状もいびつになる
。図2(A),(B) は従来例を説明する断面図であ
る。On the other hand, if an attempt is made to completely dissolve the polyimide film on the scribe line, the size of the opening on the bonding pad will increase by about 2 μm and the shape will become distorted. FIGS. 2A and 2B are cross-sectional views illustrating a conventional example.
【0007】図2(A) において,1はシリコン(S
i)ウエハ,2は1層目Al配線, 3は層間絶縁膜で
りん珪酸ガラス(PSG) 膜, 4は2層目Al配線
, 5はカバー絶縁膜でPSG 膜, 6は保護膜でポ
リイミド膜,7はパッド窓開口のためのレジスト膜であ
る。In FIG. 2(A), 1 is silicon (S
i) Wafer, 2 is the first layer Al wiring, 3 is the interlayer insulating film, which is a phosphosilicate glass (PSG) film, 4 is the second layer Al wiring, 5 is the cover insulating film, which is a PSG film, and 6 is the protective film, which is a polyimide film. , 7 are resist films for pad window openings.
【0008】ここで,Al配線2,4はボンディングパ
ッドである。PSG 膜5は通常のリソグラフィを用い
てパッド窓が開口されて2層目Al配線4の表面が露出
されている。その上にポリイミド膜6が回転塗布されて
いる。[0008] Here, the Al wirings 2 and 4 are bonding pads. A pad window is opened in the PSG film 5 using ordinary lithography, and the surface of the second layer Al wiring 4 is exposed. A polyimide film 6 is spin-coated thereon.
【0009】その上にレジスト膜7を被着し,投影露光
または密着露光によりボンディングパッド部を露光する
。図2(B) において,露光後,アルカリ現像液でパ
ッド窓開口部のレジスト膜7を溶解するとともにポリイ
ミド膜6も同じ現像液で溶解させる。A resist film 7 is deposited thereon, and the bonding pad portion is exposed by projection exposure or contact exposure. In FIG. 2B, after exposure, the resist film 7 at the pad window opening is dissolved with an alkaline developer, and the polyimide film 6 is also dissolved with the same developer.
【0010】このとき,ボンディングパッド部のポリイ
ミド膜6の塗布膜厚はカバーPSG 膜5上より厚く付
着しており,多層配線の層数が変わるたびにポリイミド
膜6の溶解時間が変わることになる。At this time, the coating thickness of the polyimide film 6 on the bonding pad portion is thicker than that on the cover PSG film 5, and the dissolution time of the polyimide film 6 changes each time the number of layers of the multilayer wiring changes. .
【0011】また,上記のようにスクライブライン等の
深い部分にポリイミド膜6が残ってしまう。Furthermore, as described above, the polyimide film 6 remains in deep parts such as scribe lines.
【0012】0012
【発明が解決しようとする課題】そのため,ポリイミド
膜をウエハ内およびデバイスの品種間で同一膜厚で被着
することが必要となる。[Problems to be Solved by the Invention] Therefore, it is necessary to deposit a polyimide film with the same thickness within the wafer and between different types of devices.
【0013】本発明は保護膜をウエハ内および品種間で
同一膜厚で被着できるようにし,特にボンディングパッ
ド部における保護膜の開口寸法の均一性とその形状の安
定化をはかることを目的とする。The purpose of the present invention is to enable a protective film to be deposited with the same thickness within a wafer and between different types of wafers, and in particular to stabilize the opening dimensions and shape of the protective film in the bonding pad area. do.
【0014】[0014]
【課題を解決するための手段】上記課題の解決は,半導
体基板(1) 上に導電膜からなるボンディングパッド
(4)を形成する工程と,該ボンディングパッド(4)
を覆ってカバー絶縁膜(5) を該基板上に被着する工
程と,該カバー絶縁膜(5) にボンディングパッド窓
を開口して該ボンディングパッド(4)の表面を露出さ
せる工程と,次いで該基板上にスピンオングラス膜(8
) を塗布して該基板の表面を平坦化する工程と,次い
で該基板上にポリイミド膜(6) を被着する工程と,
該ボンディングパッド窓上の該ポリイミド膜(6) と
該スピンオングラス膜(8) を開口する工程とを有す
ることを特徴とする半導体装置の製造方法により達成さ
れる。[Means for Solving the Problem] The above problem is solved by forming a bonding pad (4) made of a conductive film on a semiconductor substrate (1), and forming the bonding pad (4) on a semiconductor substrate (1).
a step of depositing a cover insulating film (5) on the substrate, a step of opening a bonding pad window in the cover insulating film (5) to expose the surface of the bonding pad (4); A spin-on glass film (8
) to planarize the surface of the substrate, and then depositing a polyimide film (6) on the substrate.
This is achieved by a method for manufacturing a semiconductor device characterized by comprising a step of opening the polyimide film (6) on the bonding pad window and the spin-on glass film (8).
【0015】[0015]
【作用】本発明はSOG 膜の回転塗布による平坦化を
行った後ポリイミド膜を基板上均一の厚さに被着するこ
とにより,ポリイミド膜のエッチング条件をウエハ上で
均一化したものである。[Operation] The present invention makes the etching conditions of the polyimide film uniform on the wafer by applying the polyimide film to a uniform thickness on the substrate after flattening the SOG film by spin coating.
【0016】この結果, ボンディングパッド窓を精度
よく開口でき, スクライブライン等基板上の深い部分
の残渣を残すことなくポリイミド膜のエッチングができ
るようになった。As a result, the bonding pad window can be opened with high precision, and the polyimide film can be etched without leaving residues on deep parts of the substrate such as scribe lines.
【0017】なお,SOG 膜とポリイミド膜の組み合
わせは,信頼性上耐湿性に問題なく,従来のポリイミド
膜単独の場合と相違ないことを確かめた結果採用したも
のである。なお,SOG 膜の平坦部での厚さをできる
だけ薄く塗布すればさらに効果的である。The combination of the SOG film and the polyimide film was adopted after confirming that there was no problem in terms of reliability and moisture resistance, and that it was no different from the conventional case of using a polyimide film alone. Note that it is more effective if the thickness of the SOG film on the flat part is as thin as possible.
【0018】[0018]
【実施例】図1 (A)〜(B) は本発明の一実施例
を説明する断面図である。図1(A) において,1は
Siウエハ,2は厚さ4000Åの1層目Al配線,
3は層間絶縁膜で厚さ1μmのPSG 膜, 4は厚さ
7000Åの2層目Al配線, 5はカバー絶縁膜で厚
さ1μmのPSG 膜, 6は保護膜で厚さ1μmのポ
リイミド膜,7はパッド窓開口のための厚さ4μmのレ
ジスト膜,8は平坦化膜でスピンオングラス(SOG)
膜である。Embodiment FIGS. 1A and 1B are cross-sectional views illustrating an embodiment of the present invention. In Fig. 1(A), 1 is a Si wafer, 2 is a first layer Al wiring with a thickness of 4000 Å,
3 is an interlayer insulating film, which is a 1 μm thick PSG film, 4 is a 7000 Å thick second layer Al wiring, 5 is a cover insulating film, which is a 1 μm thick PSG film, 6 is a protective film, which is a 1 μm thick polyimide film, 7 is a resist film with a thickness of 4 μm for pad window opening, and 8 is a flattening film made of spin-on glass (SOG).
It is a membrane.
【0019】ここで,Al配線2,4はボンディングパ
ッドである。PSG 膜5は通常のリソグラフィを用い
てパッド窓が開口されて2層目Al配線4の表面が露出
される。
その上にカバー絶縁膜5上での厚さが3000ÅのSO
G 膜8が回転塗布され,基板表面は平坦化されている
。Here, the Al wirings 2 and 4 are bonding pads. A pad window is opened in the PSG film 5 using ordinary lithography, and the surface of the second layer Al wiring 4 is exposed. On top of that, an SO layer with a thickness of 3000 Å is formed on the cover insulating film 5.
G film 8 is spin coated and the substrate surface is flattened.
【0020】さらにその上にレジスト膜7を被着し,投
影露光または密着露光によりボンディングパッド部を露
光する。図2(B) において,露光後,アルカリ現像
液でパッド窓開口部のレジスト膜7を溶解するとともに
ポリイミド膜6も同じ現像液で溶解させる。Further, a resist film 7 is deposited thereon, and the bonding pad portion is exposed by projection exposure or contact exposure. In FIG. 2B, after exposure, the resist film 7 at the pad window opening is dissolved with an alkaline developer, and the polyimide film 6 is also dissolved with the same developer.
【0021】ついで,現像後の残ったレジスト膜7をマ
スクにして CF4/CHF3/O2(100/100
/50 SCCM) のガスにより準異方性エッチング
を行ってSOG 膜8を開口し,その後, O2プラズ
マアッシングによりレジスト膜7を除去する。Next, using the resist film 7 remaining after development as a mask, CF4/CHF3/O2 (100/100
SOG film 8 is opened by performing quasi-anisotropic etching using a gas of /50 SCCM), and then resist film 7 is removed by O2 plasma ashing.
【0022】図2(C) は以上の工程を経てポリイミ
ド膜6とSOG 膜8が開口されたパッド部を示す。FIG. 2C shows the pad portion in which the polyimide film 6 and the SOG film 8 have been opened through the above steps.
【0023】[0023]
【発明の効果】保護膜をウエハ内および品種間で同一膜
厚で被着できるようになり,ウエハ上の深い部分に残渣
が残ることなく, 安定して保護膜のエッチング処理が
行えるようになった。[Effects of the invention] The protective film can now be deposited with the same thickness within the wafer and between different types, and the protective film can now be etched stably without leaving any residue deep on the wafer. Ta.
【0024】特にボンディングパッド部における保護膜
の開口寸法の均一性とその形状の安定化が達成された。
この結果, チップ上に耐湿性の優れた安定した保護膜
が形成できるようになり, 半導体装置の信頼性向上に
寄与することができた。[0024] In particular, the uniformity of the opening size and the stability of the shape of the protective film in the bonding pad portion were achieved. As a result, it became possible to form a stable protective film with excellent moisture resistance on the chip, contributing to improved reliability of semiconductor devices.
【図1】 本発明の一実施例を説明する断面図[Fig. 1] Cross-sectional view explaining one embodiment of the present invention
【図2
】 従来例を説明する断面図[Figure 2
] Cross-sectional view explaining a conventional example
1 Siウエハ 2 1層目Al配線 3 層間絶縁膜でPSG 膜 4 2層目Al配線 5 カバー絶縁膜でPSG 膜 6 保護膜でポリイミド膜 7 レジスト膜 8 平坦化膜でSOG 膜 1 Si wafer 2 1st layer Al wiring 3. PSG film as interlayer insulation film 4 2nd layer Al wiring 5 PSG film as cover insulating film 6 Polyimide film as a protective film 7 Resist film 8 SOG film with flattening film
Claims (1)
るボンディングパッド(4)を形成する工程と,該ボン
ディングパッド(4)を覆ってカバー絶縁膜(5) を
該基板上に被着する工程と,該カバー絶縁膜(5) に
ボンディングパッド窓を開口して該ボンディングパッド
(4)の表面を露出させる工程と,次いで該基板上にス
ピンオングラス膜(8) を塗布して該基板の表面を平
坦化する工程と,次いで該基板上にポリイミド膜(6)
を被着する工程と,該ボンディングパッド窓上の該ポ
リイミド膜(6) と該スピンオングラス膜(8) を
開口する工程とを有することを特徴とする半導体装置の
製造方法。1. A step of forming a bonding pad (4) made of a conductive film on a semiconductor substrate (1), and depositing a cover insulating film (5) on the substrate to cover the bonding pad (4). a step of opening a bonding pad window in the cover insulating film (5) to expose the surface of the bonding pad (4), and then applying a spin-on glass film (8) on the substrate to form a bonding pad window on the substrate. A step of flattening the surface and then depositing a polyimide film (6) on the substrate.
A method for manufacturing a semiconductor device, comprising the steps of: depositing a polyimide film (6) on the bonding pad window and opening the spin-on glass film (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1614691A JPH04255252A (en) | 1991-02-07 | 1991-02-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1614691A JPH04255252A (en) | 1991-02-07 | 1991-02-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04255252A true JPH04255252A (en) | 1992-09-10 |
Family
ID=11908362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1614691A Withdrawn JPH04255252A (en) | 1991-02-07 | 1991-02-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04255252A (en) |
-
1991
- 1991-02-07 JP JP1614691A patent/JPH04255252A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980514 |