JPH0425632B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sampling frequency identification method for identifying a sampling frequency from a signal having a frequency corresponding to the sampling frequency.

For example, in a magnetic recording and reproducing device that processes PCM signals sampled and encoded at different sampling frequencies in the same signal processing system and records them magnetically, the signal is supplied from external device A to magnetic recording and reproducing device B as shown in Figure 1. PCM signal D _A and corresponding
When a signal (herein referred to as a sampling frequency identification signal) S having a frequency corresponding to the frequency of the sampling signal for the PCM signal D _A is supplied, the sampling frequency identification signal S
It is necessary to identify the sampling frequency of the PCM signal _DA from .

This is to control the signal processing speed of the signal processing system in accordance with the sampling frequency, and to generate a running speed signal that serves as a reference for the magnetic tape running speed during recording.

The present invention is conceived in view of the above,
It is an object of the present invention to provide a sampling frequency identification method in an electronic device that is supplied with a PCM signal and a sampling frequency identification signal for the PCM signal and processes the PCM signal.

The present invention provides a control means for controlling passage or non-passage of the sampling frequency identification signal by a first signal having a period longer than the period of the sampling frequency identification signal, and the rise of the sampling frequency identification signal that has passed through the control means. Alternatively, the falling edge is counted and the sampling frequency is discriminated from this counted value.

The present invention will be explained below using examples.

FIG. 2 is a block diagram of an embodiment to which the method of the present invention is applied, and FIG. 3 is a specific circuit diagram of the embodiment shown in FIG.

This embodiment exemplifies the case where the present invention is applied to a digital audio tape recorder.

The sampling frequency discrimination circuit shown in FIG. 2 is provided in a digital audio tape recorder, and includes a switch means _S0 for gating the sampling frequency discrimination signal S, and a sampling frequency discrimination signal S outputted through the switch means _S0 . A counter 1 for counting rising edges, a discrimination window means 2 for discriminating whether the output of the counter 1 is within a predetermined value, a control signal generating circuit 3 controlled by the output of the discrimination window means 2, a master oscillator 4, a master oscillator 4 It consists of a frequency divider 5 which divides the output frequency of the master oscillator 4 and controls the opening and closing of the switch means _S0 with its output, and a control circuit 6 which switches the output frequency of the master oscillator 4 under the control of the output of the control signal generating circuit 3. There is. Note that 7 is an abnormality display means.

The output of the master oscillator 4 and/or the frequency divider 5 is supplied as a signal corresponding to the sampling frequency to each circuit such as a signal processing circuit.

The switch means S ₀ is closed when the control signal C _i is at a high potential and opened when the control signal C _i is at a low potential.

In one embodiment to which the method of the present invention configured as described above is applied, it is assumed that the sampling frequency identification signal S is supplied to the switch means _S0 . It is now assumed that there are three types of sampling frequencies: f _S1 , f _S2 , and f _S3 .

In order to find the sampling frequency, the control circuit 6 instructs the master oscillator 4 to oscillate at a certain frequency corresponding to one sampling frequency. Let us now assume that the one sampling frequency mentioned above is f _S1 .
This instruction from the control circuit 6 is output at a predetermined cycle only for a predetermined period necessary for each half of the sampling frequency. Further, the period of the oscillation signal of the master oscillator 4 is set to be longer than the period of the sampling frequency identification signal.

The oscillation output of the master oscillator 4 is supplied to the frequency divider 5, frequency-divided, and supplied to the switch means _S0 as a control signal for controlling the opening and closing of the switch means _S0 .

The switch means _S0 is closed while the output from the frequency divider 5 is at a high potential, and the sampling frequency identification signal S is supplied to the counter 1. The counter 1 counts the rise or fall of the input sampling frequency identification signal S, and the counted value is supplied to the discrimination window means 2. The discrimination window means 2 detects whether the count value of the counter 1 is within the discrimination window of the discrimination window means 2,
When the count value of the counter 1 is within the discrimination window, an output is supplied to the control signal generation circuit 3.

A control signal generation circuit 3 supplied with an output from the discrimination window means 2 supplies a signal to a frequency divider 5 and a control circuit 6. From the control signal circuit 3,
When no signal is supplied within the period instructed by the control circuit 6, the control circuit 6 instructs oscillation at a certain frequency corresponding to the next sampling frequency _fs2 ,
Repeat the same operation as above. This process is repeated until the count value of the counter 1 is within the discrimination window of the discrimination window means 2.

When the count value of the counter 1 is within the discrimination window of the discrimination window means 2, the control signal generation circuit 3 generates a signal within the period instructed by the control circuit 6, and the control circuit 6 receives this signal. stops switching the oscillation frequency of the master oscillator 4. Therefore, the oscillation output output from the master oscillator 4 has a frequency corresponding to the oscillation output selected.

If, as mentioned above, the sampling frequency f _S1 ,
If the count value of the counter 1 does not exist within the discrimination window of the discrimination window means 2 even after repeating a series of actions corresponding to f _S2 and f _S3 , the control circuit 6 supplies an output to the abnormality display means 7 to display an abnormality. do.

Furthermore, even if the sampling frequency is determined as described above, the control circuit 6 may switch to the PCM signal D _A with a different sampling frequency, so the control circuit 6 starts determining the sampling frequency again at a predetermined period, and has the same effect as above. repeat.

Next, the specific circuit of the embodiment shown in FIG. 2 will be explained (see FIG. 3). For explanation of this specific circuit, the sampling frequency is f _S1 = 32 KHz, f _S2 = 44.1 KHz, f _S3 = 48KHz 3
type, output from frequency divider 5 and switch means S ₀
The frequency of the signal supplied as control signal C _i to is 32
Hz, 44.1Hz, 48Hz, discrimination window means 2
The center of the discrimination window is 500 counts. In addition, sampling frequency 32KHz, 44.1KHz, 48KHz is sent from external device A as sampling frequency identification signal S.
A signal having a frequency corresponding to the sampling frequency is supplied to each of the sampling frequencies. In this example, the center of the discrimination window is set to 500 counts, so the frequency of the sampling frequency identification signal is 32KHz (32Hz x 500 x
2), 44.1KHz (44.1Hz×500×2), 48KHz (48×
500×2), which is the same as the sampling frequency.

The counter 1 includes a switch circuit _S1 to which the sampling frequency identification signal supplied from the switch means S0 is supplied, and a decimal counter ₁ that divides the frequency _of the sampling frequency identification signal output from the switch circuit S1.
1. Consists of a 64-decimal counter 12 that counts the output of the decimal counter 11, and a delay circuit 13 that delays the output of the discrimination window upper limit discriminator 22 of the discrimination window means 2, which will be described later, and controls the switch circuit _S1 with the output. The switch circuit _S1 is configured to be opened when the output of the delay circuit 13 is at a high potential and closed when the output is at a low potential.

The discrimination window means 2 is a discrimination window lower limit discriminator 2 consisting of an AND circuit to which the output of the 64-decimal counter 12 is supplied.
1. A discrimination window upper limit discriminator 22 consisting of an AND circuit to which the output of the 64-decimal counter 12 is supplied; a delay circuit 24 that delays the output of the discrimination window lower limit discriminator 21; and the output of the delay circuit 24 is supplied as a latch pulse for discrimination. It consists of a latch circuit 23 that latches the output of the window lower limit discriminator 21, and the discrimination window lower limit discriminator 21 generates an output when the count value of the 64-decimal counter 12 reaches 48, and the discrimination window upper limit discriminator 21 generates an output when the count value of the 64-decimal counter 12 reaches 48. 22 is
It is configured to generate an output when the count value of the 64-decimal counter 12 reaches 52.

The control signal generation circuit 3 includes AND gates 31, 32, 35, a latch circuit 33, and a delay circuit 3.
The output of the latch circuit 23 and the output of the discrimination window upper limit discriminator 22 are inverted and supplied to the AND gate 31, and the output of the AND gate 31 and the frequency divider 5
The output of the selection switch _S5 , that is, the inverted output of the selection switch S5, is supplied to an AND gate 32.The output of the AND gate 32 is supplied to a delay circuit 34 and a latch circuit 33, and the output of the delay circuit 34 is used as a latch pulse to be output to the AND gate. The output of 32 is latched. Further, the AND gate 35 is supplied with a discrimination start instruction signal from the control circuit 6 and an output obtained by inverting the output of a frequency dividing circuit 51 (described later), and the output of the AND gate 35 and the output of the differentiating circuit 8 are supplied to an OR gate 36. Or Gate 36
The output of the latch circuit 33 is arranged to reset the latch circuit 33.

The master oscillator 4 consists of oscillators 41, 42, 43 and a selection switch _S4 that selects and outputs one of the outputs of the oscillators 41, 42, 43, and the selection switch _S4 is controlled by the output from the control circuit 6. It is configured so that Here, the oscillators 41, 4
2 and 43 are sampling frequencies f _S1 , f _S2 , and
f Performs oscillation at a frequency corresponding to _S3 .

The frequency divider 5 consists of a frequency divider circuit 51 that frequency divides the output of the master oscillator 4 and _a selection switch S ₅ that selectively outputs the output of the frequency divider circuit 51. The selection switch S5 is configured to be switched by the output, that is, the output of the latch circuit 33, and the output of the selection switch _S5 is supplied to the switching means _S0 as a control signal _Ci , and also to the differentiating circuit 8. The output of differentiator circuit 8 is 10
It is supplied to the base counter 11, the base 64 counter 12, and the latch circuit 23 as a reset signal. Note that the output of the latch circuit 33 is supplied to the control circuit 6 as the output of the control signal generation circuit 3.

In the specific circuit shown in FIG. 3, a discrimination operation start signal (high potential output) is applied from the control circuit 6 to the AND gate 35. Simultaneously with the discrimination operation start signal, a control signal for selecting the output of the oscillator 41, for example, is supplied from the control circuit 6 to the selection switch _S4 . Therefore, the oscillation output of the oscillator 41 is supplied to the frequency dividing circuit 51 via the selection switch _S4 , and is frequency-divided. The frequency of the output of the frequency dividing circuit 51 is 32Hz. The output of the frequency dividing circuit 51 is inverted and supplied to the AND gate 35, and when the output of the frequency dividing circuit 51 changes to a low potential or is at a low potential, the OR gate 35
A reset signal is supplied to the latch circuit 33 via 6. Since the latch circuit 33 is reset _, the output of the latch circuit 33 becomes a low potential, and the selection switch _S5 is switched to the e side contact position shown in FIG. and is supplied to the switch means _S0 . Then, when the output of the frequency divider circuit 51 changes to a high potential, the switch means _S0 is closed by the output of the frequency divider circuit 51. At the same time, the rising edge of the output of the frequency dividing circuit 51 is differentiated by the differentiating circuit 8, and the decimal counter 1 is determined by this differentiated output.
1, 64-decimal counter 12, latch circuit 23 and 3
3 is reset.

The rising edge of the sampling frequency identification signal S supplied to the switch means _S0 is counted by the decimal counter 11, and the decimal counter 11 generates an output every time it is counted by 10. The output of the decimal counter 11 is counted by the 64-decimal counter 12.

When the count value of the 64-decimal counter 12 reaches "48", the output of the discrimination window lower limit discriminator 21 changes from a low potential to a high potential and is latched by the latch circuit 23. Here, the delay circuit 24 is provided to delay the output of the discrimination window lower limit discriminator 21 by a short period of time to ensure that the high potential output of the discrimination window lower limit discriminator 21 is latched by the latch circuit 23. The Q output of latch circuit 23 remains at a high potential until latch circuit 23 is next reset. When the count value of the 64-decimal counter 12 further increases and reaches 52, the output of the discrimination window upper limit discriminator 22 changes from a low potential to a high potential, and the high potential output of the discrimination window upper limit discriminator 22 is transferred to the delay circuit 13. The signal is delayed by a slight time and then supplied to the switch circuit _S1 . The switch circuit _S1 to which the high potential output is supplied from the delay circuit 13 is controlled to be in an open state.
Therefore, even if the sampling frequency identification signal S is thereafter supplied via the switch means _S0 ,
The decimal counter 11 does not count, the output of the discrimination window upper limit discriminator 22 maintains a high potential state, and the switch circuit
_S1 remains open until the output of the discrimination window upper limit discriminator 22 returns to a low potential.

Therefore, when the count value of the counter 12 that counts the frequency of the sampling frequency identification signal is 48 or more and less than 52, the output of the latch circuit 23 is at a high potential and the output of the discrimination window upper limit discriminator 22 is at a low potential. Further, in this state, the output of the AND gate 31 becomes a high potential.

Then, when the output of the frequency dividing circuit 51 becomes a low potential, the switch means _S0 becomes open, and the gate of the AND gate 32 becomes open. However, when the count value of the counter 12 is 48 or more and less than 52, the output of the AND gate 31 is at a high potential, so the output of the AND gate 32 becomes a high potential, and the latch circuit 33 latches the output of the AND gate 32. , the Q output of the latch circuit 33 becomes high potential. Therefore, the selection switch _S5 is switched to the f side contact position,
At the same time, the control circuit 6 does not output the determination start signal until the next cycle, and the selection switch _S4 is maintained in a state in which the output of the oscillator 41 is selected.

Furthermore, when the output of the frequency dividing circuit 51 described above becomes a low potential and the switch means _S0 is returned to the open state, when the count value of the counter 12 is less than 48, the Q output of the latch circuit 23 becomes a low potential. When the count value of the counter 12 is 52 or more, the output of the latch circuit 23 is the Q output or high potential output, but the output of the discrimination window upper limit discriminator 22 is low potential, and the output of the AND gate 31 is is in a high potential state. Therefore, the Q output of the latch circuit 33 remains at a high potential, and the control circuit 6 outputs a switching signal to the selection switch _S4 after a predetermined time has elapsed, and the oscillator 41
The output of the oscillator 42 is selected instead of the output of the oscillator 42 and is supplied to the frequency dividing circuit 51.

Therefore, the determination is made in the same way as in the case where the output of the oscillator 41 described above is selected based on the output of the oscillator 42.

Further, the output of the oscillator 42 is selected and the determination is made in the same manner as above. Also, if the output of the oscillator 42 is not determined in the selected state, the oscillator 42
The output of the oscillator 43 is selected instead of the output of the oscillator 43, and the determination is made in the same manner.

When the output of the oscillator 41 is currently selected, the sampling frequency identification signals supplied to the switch means _S0 are _a1 (32KHz), _a2 (44.1KHz),
The case of a ₃ (48KHz) will be specifically explained with reference to FIG. When the sampling frequency identification signal supplied to the switch means _S0 is _a1 , the counter 1
When the count value of 2 reaches "50", the switch means _S0 becomes open, the subsequent supply of the sampling frequency identification signal to the counter 11 is cut off, and the count value of the counter 12 stops at "50". Therefore, the discrimination window lower limit discriminator 21 generates a high potential output, the discrimination window upper limit discriminator 22 remains in a low potential output state, and the Q output of the latch circuit 33 becomes a high potential, and the control circuit 6 outputs a sampling frequency. Identification signal is 32KHz
It is determined that it corresponds to the sampling frequency of . As a result, the selection switch _S4 maintains its contact position.

Further, when the sampling frequency identification signal is _a2 , if the effect of the switch circuit _S1 is ignored, the switch means _S0 is closed until the count value of the counter 12 reaches 68.9. However, the count value of counter 12 is
52, the discrimination window upper limit discriminator 22 outputs a high potential output. As a result, the switch circuit _S1 is controlled to be open, and the count value of the counter 12 is 52.
It will be held in the state. Therefore, the output of the AND gate 31 is at a low potential, and the control circuit 6 is not supplied with a high potential output from the latch circuit 33 within a predetermined period corresponding to the oscillator 41, so that the sampling frequency identification signal is for a sampling frequency of 32 KHz. It is judged that it is not. The selection switch _S4 is then switched to select the output of the oscillator 42.

Further, when the sampling frequency identification signal is _a3 , the same as when the sampling frequency identification signal is _a2 described above. Note that in this case, the count value of the counter 12 is 75 compared to 68.9.

Next, when the output of the oscillator 42 is selected, the sampling frequency identification signals supplied to the switch means _S0 are _b1 (32KHz), _b2 (44.1KHz),
The case of b ₃ (48KHz) will be explained using Fig. 4. When the sampling frequency identification signal supplied to the switch means S0 _{is b2} , when the count value of the counter 12 reaches "50", the switch means _S0 becomes open, and the subsequent sampling frequency identification signal is supplied to the counter 11. is cut off, and the count value of the counter 12 stops at "50". Therefore, the output of the oscillator 41 is selected and operates in the same manner as when the sampling frequency identification signal _a1 is supplied, and the control circuit 6 determines that the sampling frequency identification signal corresponds to a sampling frequency of 44.1 KHz.

Further, when the sampling frequency identification signal is _b1 , the switch means _S0 is opened when the count value of the counter 12 reaches 36.2. Therefore, the discrimination window lower limit discriminator 21 does not generate a high potential output, and the AND gate 31 does not generate a high potential output.

Further, when the sampling frequency identification signal is _b3 , if the effect of the switch circuit _S1 is ignored, the switch means _S0 is closed until the count value of the counter 12 reaches 54.4. However, the count value of counter 12 is 52
When , the discrimination window upper limit discriminator 22 outputs a high potential output. As a result, the switch circuit _S1 is controlled to be in an open state, and the count value of the counter 12 is maintained at 52. Therefore, and gate 3
An output of 1 does not produce a high potential output.

Therefore, when the sampling frequency identification signal is b ₁ or b ₃ , the control circuit 6 is not supplied with the high potential output from the latch circuit 33 within the predetermined period corresponding to the oscillator 42, so the sampling frequency identification signal is set to the sampling frequency of 44.1KHz. It is determined that it is not intended for The selection switch _S4 is then switched to select the output of the oscillator 43.

Next, when the output of the oscillator 43 is selected, the sampling frequency identification signal supplied to the switch means _S0 is _C1 (32KHz), _C2 (44.1KHz).
Hz) and C ₃ (48KHz) will be explained with reference to FIG. When the sampling frequency identification signal supplied to the switch means _S0 is _C3 , when the count value of the counter 12 reaches "50", the switch means _S0 becomes open, and the subsequent sampling frequency identification signal is supplied to the counter 11. is blocked and counter 1
The count value of 2 stops at “50”. So oscillator 4
1 is selected and the sampling frequency identification signal _a1 is supplied, and the control circuit 6 determines that the sampling frequency identification signal corresponds to the sampling frequency of 48 KHz.

Further, when the sampling frequency identification signals are C ₁ and C ₂ , the switch means S ₀ is opened when the count value of the counter 12 reaches 33.3 and 49.5. Therefore, the discrimination window lower limit discriminator 21 does not generate a high potential output. Therefore, the output of the oscillator 42 is selected and operates in the same manner as in the case of the sampling frequency identification signal _b1 , and the control circuit 6 determines that the sampling frequency identification signal is not for the sampling frequency of 48 KHz.

In the above explanation, the upper limit of the window of the discrimination window means 2 is set to 520 and the lower limit to 480, but the upper limit may be set to 540 and the lower limit to 460. In this case, the discrimination window lower limit discriminator 21. The discrimination window upper limit discriminator 22 may be set to generate a high potential output when the count value of the counter 12 becomes 46, 54 or more.

As explained above, according to the method of the present invention, there is provided a control means for controlling passage or non-passage of the sampling frequency identification signal by a signal having a period longer than the period of the sampling frequency identification signal, and the sampling frequency identification signal passing through the control means is provided. Since the rise or fall of the signal is counted and the sampling frequency is discriminated from this count value, the sampling frequency can be easily identified. Furthermore, the maximum discrimination window width can be appropriately determined depending on the period of the signal that controls opening and closing of the control means, and/or the discrimination window means can be optimized by changing the window width of the discrimination window. Frequency discrimination can also be performed reliably. Also, the configuration is simple.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining the transfer of signals between devices. FIG. 2 is a block diagram of an embodiment to which the method of the present invention is applied. FIG. 3 is a block diagram showing a specific configuration of an embodiment to which the method of the present invention is applied. FIG. 4 is an explanatory diagram of the operation of the specific configuration example of the embodiment of the present invention shown in FIG. 3. A...External device, B...Magnetic recording/reproducing device, S...Sampling frequency identification signal, D _A ...PCM signal, S ₀
...switch means, 1...counter, 2...discrimination means,
3... Control signal generation circuit, 4... Master oscillator, 5... Frequency divider, 6... Control circuit.

Claims (1)

[Claims] 1 A PCM signal and a sampling frequency identification signal having a frequency corresponding to the frequency of the sampling signal for the PCM signal are supplied to the PCM signal.
A sampling frequency identification method in an electronic device that processes signals, the method comprising: generating a first signal having a cycle longer than the cycle of the sampling frequency identification signal; and controlling a switch means using the first signal. A sampling frequency characterized in that passing or non-passing of the sampling frequency identification signal is controlled, rising or falling edges of the sampling frequency identification signal that have passed through the switching means are counted, and the sampling frequency is discriminated from this counted value. Identification method.