JPH04258015A - Peaking suppression amplifier - Google Patents
Peaking suppression amplifierInfo
- Publication number
- JPH04258015A JPH04258015A JP3019686A JP1968691A JPH04258015A JP H04258015 A JPH04258015 A JP H04258015A JP 3019686 A JP3019686 A JP 3019686A JP 1968691 A JP1968691 A JP 1968691A JP H04258015 A JPH04258015 A JP H04258015A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- output
- detection circuit
- peaking
- error amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、ディジタル信号の矩形
波を増幅する増幅器の出力にて矩形波に生ずるピーキン
グを自動的に抑制するピーキング抑制増幅器に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peaking suppression amplifier that automatically suppresses peaking that occurs in a rectangular wave at the output of an amplifier that amplifies the rectangular wave of a digital signal.
【0002】例えば100MHzの、1レベル,0レベ
ルと変化する矩形波のディジタル信号を増幅する増幅器
の帯域は、波形を崩さない為に例えば600MHzと広
くしてある。The band of an amplifier for amplifying a rectangular digital signal of, for example, 100 MHz, which changes from 1 level to 0 level, is set to be as wide as 600 MHz, for example, in order not to destroy the waveform.
【0003】この為に、増幅器に用いるトランジスタの
特性によっては、矩形波の立ち上がり,立ち下がり時点
でピーキングを生ずる。このピーキングを手間がかから
ずに抑制出来る増幅器の提供が望まれている。For this reason, depending on the characteristics of the transistor used in the amplifier, peaking occurs at the rise and fall points of the rectangular wave. It is desired to provide an amplifier that can suppress this peaking without much effort.
【0004】0004
【従来の技術】図4は従来例のピーキング抑制増幅器の
回路図及び波形図である。図4の増幅器は(A)に示す
如き1レベルが0V,0レベルが−0.8VのECLレ
ベルの信号が入力し、出力よりは(B)に示す如き1レ
ベルが−0.8V,0レベルが−1.6VのECLレベ
ルの信号を出力するものであり、抵抗R1,R2,トラ
ンジスタTr1,Tr2,定電流源6よりなる差動増幅
器と、トランジスタTr3,抵抗R9よりなるバッフア
増幅器よりなっている。2. Description of the Related Art FIG. 4 is a circuit diagram and waveform diagram of a conventional peaking suppression amplifier. The amplifier in Figure 4 receives an ECL level signal as shown in (A) where the 1 level is 0V and the 0 level is -0.8V, and the output is -0.8V and 0 level as shown in (B). It outputs an ECL level signal with a level of -1.6V, and consists of a differential amplifier consisting of resistors R1 and R2, transistors Tr1 and Tr2, and constant current source 6, and a buffer amplifier consisting of transistor Tr3 and resistor R9. ing.
【0005】この場合、トランジスタTr1,Tr2,
Tr3の特性により(B)の出力波形に示す如く矩形波
の立ち上がり,立ち下がり時点でピーキングを生ずる事
がある。In this case, transistors Tr1, Tr2,
Due to the characteristics of Tr3, peaking may occur at the rising and falling points of the rectangular wave as shown in the output waveform in (B).
【0006】この為に、増幅器の出力に、抵抗R10,
コンデンサC3を挿入してこのピーキングを防ぐように
している。For this purpose, resistors R10 and R10 are connected to the output of the amplifier.
Capacitor C3 is inserted to prevent this peaking.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、このピ
ーキングを抑圧する抵抗R10,コンデンサC3の値を
求めるには、何回も値の違うものに取替えて、適した値
を見つけることになるので、手間がかかる問題点がある
。[Problem to be solved by the invention] However, in order to find the values of the resistor R10 and capacitor C3 that suppress this peaking, it is necessary to replace them with different values many times to find the appropriate values, which is a hassle. There are problems with this.
【0008】本発明は、自動的にピーキングを抑圧出来
るピーキング抑制増幅器の提供を目的としている。An object of the present invention is to provide a peaking suppression amplifier that can automatically suppress peaking.
【0009】[0009]
【課題を解決するための手段】図1は本発明の原理ブロ
ック図である。図1に示す如く、ディジタル信号の矩形
波を増幅する増幅器の出力に、電圧可変容量ダイオード
1を並列に接続し且つ、出力波形のピーク値を検出する
ピーク検出回路2と、出力波形の平均値を検出する平均
値検出回路3とを接続し、該ピーク検出回路2の出力と
該平均値検出回路3の出力に、該ピーク検出回路2にて
求めたピーク値と該平均値検出回路3にて求めた平均値
との差を求める第1の誤差増幅器4を接続し、更に該第
1の誤差増幅器4の出力に、該第1の誤差増幅器4にて
求めた値と、該増幅器の出力波形が正常な矩形の場合の
最大値と平均値との差の値V1との差を求める第2の誤
差増幅器5を接続し、該第2の誤差増幅器5の出力を該
電圧可変容量ダイオード1のバイアス電圧として与える
ようにする。[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. As shown in FIG. 1, a voltage variable capacitance diode 1 is connected in parallel to the output of an amplifier that amplifies a rectangular wave of a digital signal, and a peak detection circuit 2 that detects the peak value of the output waveform and the average value of the output waveform are connected in parallel. An average value detection circuit 3 that detects is connected, and the peak value obtained by the peak detection circuit 2 and the average value detection circuit 3 are connected to the output of the peak detection circuit 2 and the output of the average value detection circuit 3. A first error amplifier 4 is connected to calculate the difference between the average value obtained by the first error amplifier 4 and the output of the first error amplifier 4. A second error amplifier 5 is connected to calculate the difference between the maximum value and the average value V1 when the waveform is a normal rectangle, and the output of the second error amplifier 5 is connected to the voltage variable capacitance diode 1. Give it as a bias voltage.
【0010】0010
【作用】本発明にれば、増幅器の出力の、ピーク検出回
路2にて出力の矩形波のピーク値を検出し、又平均値検
出回路3にて出力波形の平均値を検出し、検出したピー
ク値と平均値との差を第1の誤差増幅器4にて求め第2
の誤差増幅器5に入力する。[Operation] According to the present invention, the peak value of the output rectangular wave of the output of the amplifier is detected by the peak detection circuit 2, and the average value of the output waveform is detected by the average value detection circuit 3. The difference between the peak value and the average value is determined by the first error amplifier 4 and the second
input to the error amplifier 5.
【0011】第2の誤差増幅器5では、第1の誤差増幅
器4にて求めた値と、出力のピーキングのない矩形波の
場合の最大値と平均値との差の電圧V1との差、即ち、
矩形波の最大値とピーキングにより生じたピーク値との
差の値を求め、この値の電圧を、電圧可変容量ダイオー
ド1のバイアス電圧として加えて容量を変化させ、この
差の電圧が非常に少なくなるよう,即ちピーキングによ
り生じたピーク値が殆どなくなるように自動的に制御す
る。The second error amplifier 5 calculates the difference between the value obtained by the first error amplifier 4 and the voltage V1, which is the difference between the maximum value and the average value in the case of a rectangular wave with no output peaking. ,
Find the value of the difference between the maximum value of the rectangular wave and the peak value caused by peaking, and apply this value of voltage as the bias voltage of voltage variable capacitance diode 1 to change the capacitance. In other words, the peak value caused by peaking is automatically controlled to almost disappear.
【0012】即ち、自動的にピーキングを抑制出来るの
で、ピーキングを抑制する手間をかからなくすることが
出来る。[0012] That is, since peaking can be automatically suppressed, it is possible to eliminate the trouble of suppressing peaking.
【0013】[0013]
【実施例】図2は本発明の実施例のピーキング抑制増幅
器の回路図、図3は図2の場合の1例の波形図である。Embodiment FIG. 2 is a circuit diagram of a peaking suppression amplifier according to an embodiment of the present invention, and FIG. 3 is a waveform diagram of an example in the case of FIG.
【0014】図2では、図4に示す増幅器の出力に、並
列に抵抗R11及び電圧可変容量ダイオード(バリキヤ
ップ)1を接続し、且つトランジスタTr4と、平均値
を求める抵抗R3,R4,コンデンサC1よりなる回路
を有する平均値検出回路3と、トランジスタTr5と、
ビークを求める抵抗R5,R6,ダイオードD,コンデ
ンサC2よりなる回路を有するピーク検出回路2を接続
し、平均値検出回路3,ピーク検出回路2の出力には、
ピーク検出回路2にて求めたビーク値と、平均値検出回
路3にて求めた平均値との差を求める、トランジスタT
r6,抵抗R7,R8,オペアンプ7よりなる誤差増幅
器4を接続している。In FIG. 2, a resistor R11 and a voltage variable capacitance diode (varicap) 1 are connected in parallel to the output of the amplifier shown in FIG. An average value detection circuit 3 having a circuit, a transistor Tr5,
A peak detection circuit 2 having a circuit consisting of resistors R5 and R6, a diode D, and a capacitor C2 for determining the peak is connected, and the outputs of the average value detection circuit 3 and the peak detection circuit 2 are as follows.
A transistor T that calculates the difference between the peak value determined by the peak detection circuit 2 and the average value determined by the average value detection circuit 3.
An error amplifier 4 made up of R6, resistors R7 and R8, and an operational amplifier 7 is connected.
【0015】又誤差増幅器4の出力には、誤差増幅器4
の出力と、ピーキングのない増幅器の出力の矩形波の場
合の最大値と平均値との差の電圧V1の電圧を与える電
源V3との差を求めるオペアンプ8を有する誤差増幅器
5を接続し、誤差増幅器5の出力を、バイアス電圧とし
て電圧可変容量ダイオード1に与えるようにしている。Further, the output of the error amplifier 4 is connected to the error amplifier 4.
An error amplifier 5 having an operational amplifier 8 is connected to calculate the difference between the output of the amplifier and the power supply V3 which provides the voltage V1 which is the difference between the maximum value and the average value in the case of a rectangular wave output of the amplifier without peaking. The output of the amplifier 5 is applied to the voltage variable capacitance diode 1 as a bias voltage.
【0016】図4の従来例の場合と同じく、図3(A)
に示す如きECLレベルの矩形波が入力し、増幅器の出
力には図3(B)に示す如き−0.4Vのピーキングが
生じた矩形波となったとして、図2の場合の各部の値を
図3の波形図を用いて説明する。As in the case of the conventional example shown in FIG.
Assuming that a rectangular wave with an ECL level as shown in Figure 2 is input, and the output of the amplifier becomes a square wave with peaking of -0.4V as shown in Figure 3(B), the values of each part in the case of Figure 2 are This will be explained using the waveform diagram in FIG.
【0017】ピーク検出回路2ではピーク値の−0.4
Vを検出し、平均値検出回路3では平均値の−1.2V
を検出して誤差増幅器4に入力し、誤差増幅器4では差
の0.8Vを求め誤差増幅器5の一方の入力に入力する
。The peak detection circuit 2 detects -0.4 of the peak value.
V is detected, and the average value detection circuit 3 detects the average value of -1.2V.
is detected and inputted to the error amplifier 4, which calculates the difference of 0.8V and inputs it to one input of the error amplifier 5.
【0018】誤差増幅器5の他方の入力には、図3(C
)に示す如きピーキングの生じていない矩形波の平均値
−1.2Vと最大値−0.8Vとの差の0.4Vを予め
求め、電源V3より加えてあるので、出力は差の0.4
Vとなり、この電圧が電圧可変容量ダイオード1のバイ
アス電圧として与えられ、電圧可変容量ダイオード1の
容量が大きくなり、ピーク値が低くなり、誤差増幅器5
の出力電圧は小さくなる。The other input of the error amplifier 5 has the signal shown in FIG.
) The difference between the average value -1.2V and the maximum value -0.8V of the rectangular wave with no peaking as shown in 0.4V is determined in advance and added from the power supply V3, so the output is 0.4V of the difference. 4
V, this voltage is given as the bias voltage of the voltage variable capacitance diode 1, the capacitance of the voltage variable capacitance diode 1 increases, the peak value becomes low, and the error amplifier 5
output voltage becomes smaller.
【0019】このような動作を繰り返しピーク値がなく
なると、誤差増幅器5の出力電圧は0となるので、この
点で電圧可変容量ダイオード1の容量値の変化は停まる
。即ち、自動的にピーキングを抑制出来るので手間のか
かるのをなくすることが出来る。When the peak value disappears by repeating such an operation, the output voltage of the error amplifier 5 becomes 0, and at this point, the change in the capacitance value of the voltage variable capacitance diode 1 stops. In other words, since peaking can be automatically suppressed, time and effort can be eliminated.
【0020】[0020]
【発明の効果】以上詳細に説明せる如く本発明によれば
、自動的にピーキングを抑制出来るピーキング抑制増幅
器が得られ、ピーキングを抑制する手間が省ける効果が
ある。As described in detail above, according to the present invention, a peaking suppression amplifier capable of automatically suppressing peaking can be obtained, and the effort of suppressing peaking can be saved.
【図1】は本発明の原理ブロック図、FIG. 1 is a block diagram of the principle of the present invention.
【図2】は本発明の実施例のピーキング抑制増幅器の回
路図、FIG. 2 is a circuit diagram of a peaking suppression amplifier according to an embodiment of the present invention;
【図3】は図2の場合の1例の波形図、[Fig. 3] is an example waveform diagram in the case of Fig. 2;
【図4】は従来
例のピーキング抑制増幅器の回路図及び波形図、FIG. 4 is a circuit diagram and waveform diagram of a conventional peaking suppression amplifier;
1は電圧可変容量ダイオード、 2はピーク検出回路、 3は平均値検出回路、 4、5は誤差増幅器、 6は定電流源、 7,8はオペアンプ、 Tr1〜Tr6はトランジスタ、 R1〜R10は抵抗、 C1〜C3はコンデンサ、 Dはダイオード、 V3は電源を示す。 1 is a voltage variable capacitance diode, 2 is a peak detection circuit; 3 is an average value detection circuit; 4 and 5 are error amplifiers, 6 is a constant current source, 7 and 8 are operational amplifiers, Tr1 to Tr6 are transistors, R1 to R10 are resistors, C1 to C3 are capacitors, D is a diode, V3 indicates a power supply.
Claims (1)
幅器の出力に、電圧可変容量ダイオード(1)を並列に
接続し且つ、出力波形のピーク値を検出するピーク検出
回路(2)と、出力波形の平均値を検出する平均値検出
回路(3)とを接続し、該ピーク検出回路(2)の出力
と該平均値検出回路(3)の出力に、該ピーク検出回路
(2)にて求めたピーク値と該平均値検出回路(3)に
て求めた平均値との差を求める第1の誤差増幅器(4)
を接続し、更に該第1の誤差増幅器(4)の出力に、該
第1の誤差増幅器(4)にて求めた値と、該増幅器の出
力波形が正常な矩形の場合の最大値と平均値との差の値
(V1)との差を求める第2の誤差増幅器(5)を接続
し、該第2の誤差増幅器(5)の出力を該電圧可変容量
ダイオード(1)のバイアス電圧として与えるようにし
たことを特徴とするピーキング抑制増幅器。1. A peak detection circuit (2) that connects a voltage variable capacitance diode (1) in parallel to the output of an amplifier that amplifies a rectangular wave of a digital signal, and detects the peak value of the output waveform; An average value detection circuit (3) that detects the average value of is connected to the output of the peak detection circuit (2) and the output of the average value detection circuit (3). a first error amplifier (4) that calculates the difference between the peak value obtained by the calculation and the average value obtained by the average value detection circuit (3);
and further connect the output of the first error amplifier (4) to the value obtained by the first error amplifier (4), the maximum value and the average when the output waveform of the amplifier is a normal rectangle. A second error amplifier (5) is connected to calculate the difference between the difference value and the value (V1), and the output of the second error amplifier (5) is used as the bias voltage of the voltage variable capacitance diode (1). A peaking suppression amplifier characterized in that it provides a peaking suppression amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3019686A JPH04258015A (en) | 1991-02-13 | 1991-02-13 | Peaking suppression amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3019686A JPH04258015A (en) | 1991-02-13 | 1991-02-13 | Peaking suppression amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04258015A true JPH04258015A (en) | 1992-09-14 |
Family
ID=12006124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3019686A Withdrawn JPH04258015A (en) | 1991-02-13 | 1991-02-13 | Peaking suppression amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04258015A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007026670A1 (en) * | 2005-09-02 | 2007-03-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
| WO2007110915A1 (en) * | 2006-03-27 | 2007-10-04 | Fujitsu Limited | Peaking control circuit |
-
1991
- 1991-02-13 JP JP3019686A patent/JPH04258015A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007026670A1 (en) * | 2005-09-02 | 2007-03-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
| US7923982B2 (en) | 2005-09-02 | 2011-04-12 | Panasonic Corporation | Semiconductor integrated circuit |
| WO2007110915A1 (en) * | 2006-03-27 | 2007-10-04 | Fujitsu Limited | Peaking control circuit |
| US7786785B2 (en) | 2006-03-27 | 2010-08-31 | Fujitsu Limited | Peaking control circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980514 |