JPH0425954A - Error processing system for memory device - Google Patents

Abstract

PURPOSE:To shorten access time by providing a switch instruction means which outputs a prescribed selection signal for selecting data which a memory outputs to a data selection means when it detects that data is not continuously read. CONSTITUTION:An error detection correction circuit 21 detects the error of inputted data but it does not output an error detection signal and outputs received data as it is to a selection circuit 22 through a path 203 when there is no error in data. The error detection correction circuit 21 detects the error of inputted data but it outputs the error detection signal when there is the error in data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error handling method for a memory device.

[Conventional technology]

In conventional error processing methods for memory devices, errors in data read from memory are corrected in the following manner. That is, each word stored in the memory is composed of data and a correction code for detecting and correcting errors, and an error detection/correction detection circuit is provided for detecting and correcting data errors based on the correction code. Each time data is read from the memory, this error detection and correction circuit receives the data and checks to see if there is an error.If there is an error, it corrects the data based on the correction code and outputs it, ensuring that there is no error. In this case, the read data is output as is to the request source.

[Problem to be solved by the invention]

In such a conventional error processing method, data read from a memory is output through an error detection and correction circuit not only when there is an error but also when there is no error. Therefore, if there are no errors in the data, the time from when the memory is accessed until the data is finally output is longer than necessary.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error handling method for a memory device that eliminates such drawbacks and reduces access time.

[Means to solve the problem]

The present invention provides an error processing method for a memory device including an error detection and correction means for detecting and correcting an error in data read from a memory. data selection means for selecting and outputting any of the corrected data based on a predetermined selection signal; continuous reading detection means for detecting whether data is being continuously read from the memory; data invalidation instruction means for outputting a predetermined signal instructing to invalidate the data when the error detection and correction means detects an error in the data read from the memory; When an error in data read from the memory is detected, the error detection and correction means outputs the predetermined selection signal for selecting the corrected data to the data selection means, and the continuous read detection means outputs the predetermined selection signal to the data selection means, switching instruction means for outputting the predetermined selection signal for selecting data to be output from the memory to the data selection means when it is detected that data is not read out continuously from the memory. shall be.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a memory device based on the error handling method of the present invention. This memory device has a 4-way interleaved configuration consisting of 4 banks, with 10~
Reference numeral 13 denotes first to fourth memories (MEM) constituting each bank.
(0) to (3)), 14 is a first selection circuit (SEL(0)) that sequentially selects and outputs the data and correction code read from these memories, and 20 is a selection circuit. A first memory read register (MRDR(1)) receives and holds data and correction codes from circuit 14;
21 is an error detection and correction circuit that detects the presence or absence of a data error from the data and correction code output by the register 20, and when an error is detected, corrects the data and outputs an error detection signal. Further, 22 receives data from the error detection and correction circuit 21 and data from the selection circuit 14 through a path 203 and a path 101, respectively, and selects either data based on a selection signal from an OR gate circuit 23, which will be described later. The second output
This is the selection circuit (SEL (1)). 30 receives data output from the selection circuit 22 through a path 207;
The second memory read data register (MRDR) holds
(2) L40 passes the data output from register 30 to pass 3.
The third memory read data register (MRDR(3)) receives and holds data through 01.

Furthermore, 24 is a continuous read detection circuit that detects whether the data from Memo January 0 to 13 is being read out continuously and outputs a predetermined signal representing the detection result, and 31 is an error detection and correction circuit 21. The data invalidation instruction means outputs a predetermined signal instructing to invalidate the data when detecting an error in data read from the memory and outputting an error detection signal. and 25 is pass 20
2, it is set when an error detection signal is received from the error detection and correction circuit 21 through the continuous readout detection circuit 24.
detects that data is not being continuously read from memory, it passes a signal representing the detection result to pass 206.
23 is an OR gate circuit (23) that outputs the output signal of this flip-flop 25 or the error detection signal from the error detection and correction circuit 21 to the selection circuit 22 through a path 204. GATE). These flip-flop 25 and gate circuit 23 constitute switching instruction means.

Next, the operation will be explained using the timing chart shown in FIG. When data is read out continuously from the memory, the timing T o ”
Data ■～■ and correction code (not shown) in Ts
Output. These data and correction codes are sequentially selected and outputted by the selection circuit 14, and the register 20 sequentially receives them at timing T I"".
'Hold for each period of T4. On the other hand, each data output from the selection circuit 14 is sent to the selection circuit 2 through the bus 101.
2 is also input.

First, at timing T1, the data (2) held in the register 20 and the correction code are input to the error detection and correction circuit 21, and the data (2) is also input to the selection circuit 22 via the bus lot. In the initial state, the selection circuit 22 selects path 1.
Since the signal from 01 is selected and output, in this case, data 2 from the selection circuit 14 is output from the selection circuit 22 as is. On the other hand, the error detection and correction circuit 21 performs error detection on the input data ■, but if the data ■ has no error, the error detection and correction circuit 21 does not output an error detection signal, and the receiver receives the received data. bus 2
03 to the selection circuit 22. However, as described above, this data is not selected by the selection circuit 22 and is discarded. Data (2) output from the selection circuit 22 is held in the register 3o at timing T, and further held in the register 4o at the next timing T2, and is output as final read data.

Next, at timing T2, the data (2) held in the register 2o and the correction code are input to the error detection and correction circuit 21, and the data (2) is also input to the selection circuit 22 via the path 101. In this state, the selection time 822 is pass 1.
Since the signal from 01 is selected and output, in this case too, the data ■ from the selection circuit 14 is output as is from the selection circuit 22, and is held in the register 30 at timing T2.
Also timing T.

It is temporarily held in the register 40. On the other hand, the error detection and correction circuit 21 performs error detection on the input data (2). If there is an error in the data (2), the error detection and correction circuit 21 outputs an error detection signal. The receiver also corrects the received data and sends it to the selection circuit 2 as data ■'.
Output to 2. The error detection signal outputted from the error detection and correction circuit 21 causes the flip-flop 25 to be set, and is also input to the selection circuit 22 through the OR gate circuit 23. The selection circuit 22 switches data to be selected by this signal, and selects and outputs the data from the error detection and correction circuit 21. Further, since the set signal of the flip-flop 25 is applied to the selection circuit 22 through the gate 23, after the middle of the timing Tt, the selection circuit 22 selects and outputs the data from the error detection and correction circuit 21. Therefore, the data ■' corrected by the error detection and correction circuit 21 is held in the register 30 at timing 3 and further in the register 40 at timing T4. Further, the error detection signal outputted by the error detection and correction circuit 21 is also given to the read data invalidation instruction means 31, and the invalidation instruction means 31 receives the read data finally output from the register 40 at timing T, that is, the data (2) Outputs a predetermined signal instructing to invalidate. At the memory access request source, when this signal is output, the data output from the register 40, that is, the data
is invalidated, and the data output at the next timing, that is, data ■', is accepted as valid data.

Next, at timing T, the data 2 held in the register 2o and the correction code are input to the error detection and correction circuit 21. The data ■ is also passed through the bus 101 to the selection circuit 2.
In this case, the selection circuit 22 selects the path 2.
Since the signal from bus 101 is selected and output, the data from bus 101 is discarded. Then, the error detection and correction circuit 21 performs error detection on the input data ■, but if there is no error in the data ■, the error detection and correction circuit 21 does not output an error detection signal and does not receive an error. The data ■ is output to the selection circuit 22 as is.

This data ■ is input from the selection circuit 22 to the register 30, and the register 30 holds it at timing T4. Furthermore, the register 40 holds data ■ at timing T, and outputs it as final read data.

Assuming that there is no error in the data 2 held in the register 20 at timing T4, it is output as is from the error detection and correction circuit 21, and is sent from the selection circuit 22 to the register 30 and then to the register 40, and is sent to the register 40 at timing T.
is held and output as the final read data. As long as data is continuously read from the memory, the data is processed and output through the register 20, error detection and correction circuit 21, selection circuit 22, and registers 30 and 40.

Next, data ■ is read out from the memory 10 at timing T4, and after that, data ■ is read out at timing T4.
, and if there is no error in any of the data, data (2) is processed in the same route as data (2), but data (2) is processed as follows. That is, the continuous readout detection circuit 24 detects that the readout is interrupted at timing T, and sends a signal representing the detection result to the flip-flop 2 via the bus 206.
Output to 5. As a result, the flip-flop 25 is reset, and since its output signal is provided to the selection circuit 22 through the OR gate circuit 23, the selection circuit 22 is switched to select and output data from the bus 101. Therefore, data ■ is bus 101, selection circuit 22
The signal is input to the register 30 via the path , held at timing T7, and then held at timing T and outputted to the register 40.

In this way, in the memory device based on the error processing method of the present invention, data is output through the error detection and correction circuit only when there is an error in the data and when data is read continuously following the error data. In a normal state where there are no errors in the data, the data is bypassed and output without passing through the error detection and correction circuit. Therefore, according to the present invention, memory access time can be shortened.

〔Effect of the invention〕

As described above, the present invention provides an error processing system for a memory device equipped with an error detection and correction means for detecting and correcting errors in data read from a memory. data selection means for selecting and outputting any of the data corrected by the detection and correction means based on a predetermined selection signal; and continuous reading detection means for detecting whether or not data is being continuously read from the memory. data invalidation instruction means for outputting a predetermined signal instructing to invalidate the data when the error detection and correction means detects an error in data read from the memory; When an error in the read data is detected, the error detection and correction means outputs a predetermined selection signal for selecting the corrected data to the data selection means, and the continuous read detection means continuously reads the data from the memory. Switching instruction means is provided for outputting a predetermined selection signal for selecting data to be outputted from the memory to the data selection means when it is detected that the data is not output.

Therefore, in the memory device based on the error processing method of the present invention, data is output through the error detection and correction means only when there is an error in the data and when data is read following the error data, and the data is free from errors. Under normal conditions, data is bypassed and output without passing through the error detection and correction circuit. Therefore, according to the present invention, memory access time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory device based on the error processing method of the present invention, and FIG. 2 is a timing chart for explaining the operation of the memory device of FIG. 1. 10 to 13... First to fourth memories (MEM (0) to (3)) 14, 22... First and second selection circuits 23, 24, 25, 31, (SEL (0) , (1)) ・First to third memory read data registers (MRDR(1) to (3)) ・OR gate circuit (GATE) ・Continuous read detection circuit/selection circuit control flip-flop (FF) ・Read data Invalidation instruction means 40・

Claims (1)

[Claims] (1) In an error processing method for a memory device equipped with an error detection and correction means for detecting and correcting an error in data read from a memory, the data read from the memory or the error detection and correction means data selection means for selecting and outputting any of the corrected data based on a predetermined selection signal; continuous reading detection means for detecting whether data is being read out continuously from the memory; data invalidation instruction means for outputting a predetermined signal instructing to invalidate the data when the detection and correction means detects an error in data read from the memory; When an error in the data read from the memory is detected, the error detection and correction means outputs the predetermined selection signal to the data selection means for selecting the corrected data, and the continuous readout detection means outputs the predetermined selection signal for selecting the corrected data from the memory. and switching instruction means for outputting the predetermined selection signal for selecting data to be output from the memory to the data selection means when it is detected that data is not read out continuously. Error handling method for memory devices.