JPH0533252U - Memory controller - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to provide a memory control device capable of high-speed data reading without disturbing the pipeline reading sequence. [Structure] When data stored in a memory is read using a pipeline method, when an error is detected in the middle of the sequence, the address of the memory at that time is stored in a register and all the data is stored. After the reading is completed, the error correction and the writing to the memory are performed on the data of the address stored in the register.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a memory control device having a data error detection / correction function when reading data stored in a memory.

[0002]

[Prior Art]

 FIG. 3 is a block diagram showing a configuration example of a conventional device. Reference numeral 1 is a memory for storing data, which is composed of a data section 1a and a check bit section 1b. The data check bit generation circuit 2 read from the memory 1 is entered, and check bits are generated. On the other hand, the check bit is also read from the memory 1 and enters the syndrome generation circuit 3. The output of the check bit generation circuit 2 is also input to the other input of the syndrome generation circuit 3.

The syndrome generation circuit 3 receives the output of the check bit generation circuit 2 and the check bit of the memory 1 and generates a syndrome (error correction code). The output of the syndrome generation circuit 3 enters the syndrome analysis circuit 4. The syndrome analysis circuit 4 receives this syndrome and estimates an error correction pattern.

The correction circuit 5 contains the data read from the memory 1. Then, the correction circuit 5 corrects the data read from the memory 1 based on the output (estimated error correction pattern) from the syndrome analysis circuit 4. Then, the corrected data is output from the correction circuit 5. Needless to say, if the data read from the memory 1 has no error, the data read from the memory 1 passes through the correction circuit 5 and is read as it is.

[0005]

[Problems to be solved by the device]

 Since it takes a certain amount of time to detect and correct the above-mentioned error, when reading data from a memory at high speed (burst transfer, for example), a pipeline method is used as shown in FIG. In other words, it is assumed that the data read processing is composed of three stages, which are a read stage, an error detection / correction stage, and an output stage, and these stages are sequentially executed by shifting one stage for each memory bank. Is the way to go. The horizontal axis represents time and the vertical axis represents the memory bank. When this pipeline method is used, it is not necessary to wait for the read processing of the next bank until the read processing of one bank is completed, so high-speed processing can be performed.

However, if an error is detected in the middle of this pipeline, a process for writing correct data to the memory 1 is started, and thus the pipelines of other lines also stop operating. When the correct data writing process is completed, the process returns to the normal process and the pipeline process is continued. Therefore, there is a problem that the pipeline movement is disturbed when an error is detected and complicated control is required.

The present invention has been made in view of the above problems, and an object thereof is to provide a memory control device capable of high-speed data reading without disturbing the pipeline reading sequence.

[0008]

[Means for Solving the Problems]

 The present invention, which solves the above-mentioned problem, stores the memory address at that time in a register when an error is detected during the sequence when the data stored in the memory is read by using the pipeline method. The feature is that after all the data reading is completed, the error correction and the writing to the memory are performed on the data of the address stored in the register.

[0009]

[Action]

 For the memory address where an error is detected in the middle of the pipeline sequence, correct data writing to the memory should be performed after all data transfer is completed. By adopting such a sequence, data can be read at high speed without disturbing the pipeline sequence.

[0010]

【Example】

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of the present invention. The same parts as those in FIG. 3 are designated by the same reference numerals. In the figure, 10 is a CPU, 11 is a bidirectional buffer connected to the CPU 10 via a data bus, and 12 is a check bit generation circuit that receives data from the bidirectional buffer 11 and generates a check bit. The output is stored in the check bit unit 1b of the memory 1.

Reference numeral 13 is a register for temporarily holding the output of the memory 1 (hereinafter referred to as A register), and 14 is a register for temporarily holding the output of the correction circuit 5 (hereinafter referred to as B register). The output of the B register is fed back to the output section of the bidirectional buffer 11.

Reference numeral 15 is a register connected to an address bus to hold a specific address as a store signal (hereinafter referred to as C register), and 16 is a register to hold a specific memory bank number as a store signal (hereinafter referred to as D register). is there. The output of the D register is combined with the output of the C register. Reference numeral 20 is a control circuit that is activated by a start signal from the CPU 10 and receives an error signal from the syndrome analysis circuit 4 to perform overall control. The store signals of the C register and the D register are output from this control circuit 20. Further, the control circuit 20 gives the number of banks to the D register.

Numeral 17 is a multiplexer which receives the output of the address bus and the register C and switches it by a select signal from the control circuit 20 to select either one. The output of the multiplexer 17 is given to the memory 1 as an address signal. The operation of the circuit configured as described above will be described below. (When CPU Writes Data in Memory 1) When the control circuit 20 receives the start signal from the CPU 10, the control circuit 20 sets the multiplexer 17 to the normal address side. Then, the data output from the CPU 10 enters the memory 1 via the buffer 11. On the other hand, the check bit generation circuit 12 generates a check bit from the data output from the CPU 10. Then, this check bit enters the memory 1. In this way, data and check bits are sequentially written in the memory 1 according to the address and bank from the multiplexer 17. (When CPU Reads Data from Memory 1 in Burst Mode) An explanation will be given according to the pipeline sequence in FIG. Upon receiving the start signal from the CPU 10, the control circuit 20 sets the multiplexer 17 on the normal address side. The control circuit 20 gives a read signal to the memory 1, and the data and the check bit at the address indicated by the address and the bank are read and held in the register A (T1 stage).

Next, when the data is normal at the error detection / correction stage, the data read from the register A is held in the register B as it is. Next, when the syndrome analysis circuit 4 detects an error, the correction circuit 5 corrects the data if correctable, holds the correct data in the register B, and notifies the control circuit 20 of the error signal. When the control circuit 20 receives this error signal, it gives a store signal to the registers C and D, and holds the address and the number of memory banks at this time in their respective registers. On the other hand, at the same time, the data of the next bank is read out and held in the register A (T2 stage).

The data held in the register B is transferred to the CPU 10. At the same time, the data read in the T2 stage enters the error detection mode, the data in the new bank is read out, and is held in the register A (T3 stage). The above sequence is repeated sequentially. In this example, after the 4-cycle transfer is completed, the erroneous data is read again from the stored error address and bank number, corrected, and then rewritten.

A specific description will be given. For example, assume that there is an error in the first cycle. At this time, the address is stored in the C register and the bank number is stored in the D register. After the 4-cycle data transfer is completed, the control circuit 20 gives a switching signal to the multiplexer 17 and gives the outputs of the C register and the D register to the memory 1, and the data at the address and the address designated by the bank is read ( T7 stage).

Then, the erroneous data is read again, analyzed by the syndrome analysis circuit 4, corrected to the original correct data by the correction circuit 5, and then stored in the register B (T8 stage). The data held in the B register is read and given to the memory 1. The control circuit 20 gives a write signal to the memory 1 to write the corrected data to the address given by the C register and the D register (T9 stage).

As described above, the present invention reads erroneous data from the memory 1 based on the address and the bank storing the erroneous data stored in the registers C and D after all the data transfer is completed, After making corrections, write again at the same address. Therefore, the data can be corrected without affecting the pipeline operation sequence. When an uncorrectable error is detected at the error detection / correction stage, the syndrome analysis circuit 4 notifies the CPU 10 of an error signal to that effect when the data is output.

[0019]

[Effect of the device]

 As described above in detail, according to the present invention, regardless of whether or not there is an error in the data, the memory address with the error is stored in the register and the burst data transfer sequence by the pipeline is continued to ensure that all data is After the transfer sequence is completed, the erroneous data is corrected and rewritten to the memory.Therefore, a memory controller that can read data at high speed without disturbing the pipeline reading sequence is provided. Can be provided.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a pipeline sequence according to the present invention.

FIG. 3 is a block diagram showing a configuration example of a conventional device.

FIG. 4 is an explanatory diagram of a pipeline data reading method.

[Description of Codes] 1 Memory 1a Data part 1b Check bit part 2 Check bit generation circuit 3 Syndrome generation circuit 4 Syndrome analysis circuit 5 Correction circuit 10 CPU 11 Bidirectional buffer 12 Check bit generation circuit 13 register 14 register 15 register 16 register 17 multiplexer 20 control circuit

Claims (1)

[Scope of utility model registration request] 1. When reading data stored in a memory using a pipeline method, when an error is detected in the middle of the sequence, the address of the memory at that time is stored in a register, and all the addresses are stored. The memory control device is characterized in that after the data reading is completed, the error correction and the writing to the memory are performed on the data of the address stored in the register.