JPH0426545U - - Google Patents
Info
- Publication number
- JPH0426545U JPH0426545U JP1990067997U JP6799790U JPH0426545U JP H0426545 U JPH0426545 U JP H0426545U JP 1990067997 U JP1990067997 U JP 1990067997U JP 6799790 U JP6799790 U JP 6799790U JP H0426545 U JPH0426545 U JP H0426545U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- board
- holes
- circuit component
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の集積回路部品の実施例を示す
分解斜視図、第２図は第１図の回路部品の裏面図
、第３図及び第４図は第１図に示した回路部品の
製造方法説明図、第５図は従来の集積回路実装方
法を説明するもので、同図ａ〜ｄは基板側面図、
同図ｅはフイルムキヤリア平面図、同図ｆは端子
枠付き集積回路をフイルムキヤリアに接合した場
合の側面図、同図ｇはそれを基板上に搭載した場
合の側面図である。
１０……端子枠付きの集積回路、２０……基板
、２１……配線パターン、２２……搭載位置、２
３……外部接続端子、２４……裁断面。
FIG. 1 is an exploded perspective view showing an embodiment of the integrated circuit component of the present invention, FIG. 2 is a back view of the circuit component shown in FIG. 1, and FIGS. 3 and 4 are views of the circuit component shown in FIG. 1. The manufacturing method explanatory diagram, FIG. 5, is for explaining the conventional integrated circuit mounting method, and the same figures a to d are side views of the board,
Figure e is a plan view of the film carrier, Figure f is a side view of the integrated circuit with a terminal frame bonded to the film carrier, and Figure G is a side view of the integrated circuit mounted on a substrate. 10... Integrated circuit with terminal frame, 20... Board, 21... Wiring pattern, 22... Mounting position, 2
3... External connection terminal, 24... Cutting surface.
Claims (1)
配し、前記各スルーホールを縦断する面で裁断し
た基板と、当該基板上に形成された配線パターン
の所定位置に実装された端子枠付き集積回路とか
ら成ることを特徴とする集積回路部品。 A board with external connection terminals consisting of through holes arranged on the periphery and cut along a plane that vertically traverses each of the through holes, and an integrated circuit with a terminal frame mounted at a predetermined position of a wiring pattern formed on the board. An integrated circuit component characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990067997U JPH0426545U (en) | 1990-06-27 | 1990-06-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990067997U JPH0426545U (en) | 1990-06-27 | 1990-06-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0426545U true JPH0426545U (en) | 1992-03-03 |
Family
ID=31602068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990067997U Pending JPH0426545U (en) | 1990-06-27 | 1990-06-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0426545U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002334951A (en) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | Semiconductor element mounting substrate and semiconductor package |
| JP2002334949A (en) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | Method for manufacturing semiconductor package and substrate for mounting semiconductor element |
| JP2002334948A (en) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | Semiconductor package, substrate for mounting semiconductor element, and method of manufacturing the same |
-
1990
- 1990-06-27 JP JP1990067997U patent/JPH0426545U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002334951A (en) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | Semiconductor element mounting substrate and semiconductor package |
| JP2002334949A (en) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | Method for manufacturing semiconductor package and substrate for mounting semiconductor element |
| JP2002334948A (en) * | 1994-03-18 | 2002-11-22 | Hitachi Chem Co Ltd | Semiconductor package, substrate for mounting semiconductor element, and method of manufacturing the same |