JPH0426546U - - Google Patents

Info

Publication number
JPH0426546U
JPH0426546U JP1990067541U JP6754190U JPH0426546U JP H0426546 U JPH0426546 U JP H0426546U JP 1990067541 U JP1990067541 U JP 1990067541U JP 6754190 U JP6754190 U JP 6754190U JP H0426546 U JPH0426546 U JP H0426546U
Authority
JP
Japan
Prior art keywords
recess
semiconductor element
accommodating
wiring layer
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990067541U
Other languages
Japanese (ja)
Other versions
JP2514094Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990067541U priority Critical patent/JP2514094Y2/en
Publication of JPH0426546U publication Critical patent/JPH0426546U/ja
Application granted granted Critical
Publication of JP2514094Y2 publication Critical patent/JP2514094Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の半導体素子収納用パツケージ
の一実施例を示す断面図、第２図ａ，ｂ，ｃは第
１図に示すパツケージの絶縁基体の製造方法を説
明するための各工程毎の断面図、第３図は従来の
半導体素子収納用パツケージの断面図、第４図は
第３図に示すパツケージの製造方法を説明するた
めの断面図である。 １……絶縁基体、１ａ……凹部、１ｂ……貫通
孔、２……蓋体、５……メタライズ配線層、７…
…外部リード端子。 FIG. 1 is a cross-sectional view showing an embodiment of the package for housing semiconductor elements of the present invention, and FIGS. 3 is a sectional view of a conventional package for housing semiconductor elements, and FIG. 4 is a sectional view for explaining a method of manufacturing the package shown in FIG. 3. DESCRIPTION OF SYMBOLS 1...Insulating base, 1a...Recess, 1b...Through hole, 2...Lid, 5...Metalized wiring layer, 7...
...External lead terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子を収容するための凹部及び半導体素
子の各電極を外部電気回路に電気的に接続するた
めのメタライズ配線層を有する絶縁基体と蓋体と
から成る半導体素子収納用パツケージにおいて、
前記メタライズ配線層が絶縁基体の凹部周辺より
凹部内壁面を経て凹部底面に導出され、且つ該凹
部底面に穿設した貫通孔を介して絶縁基体底面に
延出されていることを特徴とする半導体素子収納
用パツケージ。 A package for accommodating a semiconductor element comprising an insulating base body and a lid body having a recess for accommodating the semiconductor element and a metallized wiring layer for electrically connecting each electrode of the semiconductor element to an external electric circuit,
A semiconductor characterized in that the metallized wiring layer is led out from the periphery of the recess of the insulating substrate through the inner wall surface of the recess to the bottom surface of the recess, and extends to the bottom surface of the insulating substrate through a through hole formed in the bottom surface of the recess. Package cage for storing elements.
JP1990067541U 1990-06-26 1990-06-26 Package for storing semiconductor devices Expired - Lifetime JP2514094Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990067541U JP2514094Y2 (en) 1990-06-26 1990-06-26 Package for storing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990067541U JP2514094Y2 (en) 1990-06-26 1990-06-26 Package for storing semiconductor devices

Publications (2)

Publication Number Publication Date
JPH0426546U true JPH0426546U (en) 1992-03-03
JP2514094Y2 JP2514094Y2 (en) 1996-10-16

Family

ID=31601200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990067541U Expired - Lifetime JP2514094Y2 (en) 1990-06-26 1990-06-26 Package for storing semiconductor devices

Country Status (1)

Country Link
JP (1) JP2514094Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251488A (en) * 1998-03-05 1999-09-17 Sumitomo Metal Electronics Devices Inc Ceramic package
JP2001110941A (en) * 1999-10-06 2001-04-20 Meito Chin Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63261862A (en) * 1987-04-20 1988-10-28 Sumitomo Electric Ind Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63261862A (en) * 1987-04-20 1988-10-28 Sumitomo Electric Ind Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11251488A (en) * 1998-03-05 1999-09-17 Sumitomo Metal Electronics Devices Inc Ceramic package
JP2001110941A (en) * 1999-10-06 2001-04-20 Meito Chin Semiconductor device

Also Published As

Publication number Publication date
JP2514094Y2 (en) 1996-10-16

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term