JPH0452996Y2 - - Google Patents
Info
- Publication number
- JPH0452996Y2 JPH0452996Y2 JP1987096416U JP9641687U JPH0452996Y2 JP H0452996 Y2 JPH0452996 Y2 JP H0452996Y2 JP 1987096416 U JP1987096416 U JP 1987096416U JP 9641687 U JP9641687 U JP 9641687U JP H0452996 Y2 JPH0452996 Y2 JP H0452996Y2
- Authority
- JP
- Japan
- Prior art keywords
- carrier body
- bonding land
- cavity
- stepped
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
（産業上の利用分野）
本考案は半導体素子を収容する多層チツプキヤ
リアに関する。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a multilayer chip carrier for accommodating semiconductor devices.
（従来の技術）
従来、この種の多層チツプキヤリアは、第４図
乃至第６図示の如く、キヤリア本体ａの中央部に
半導体素子ｂの収納用キヤビテイｃを形成すると
共に該キヤビテイｃ内の外周に沿つて形成された
段部ｄの上面ｅにボンデイングランドｆを配設
し、該キヤリア本体ａ内に複数層の内部電極ｇを
設け、該キヤリア本体ａの外側面ｈに外部接続用
端子ｉを配設して成るを一般とする。(Prior Art) Conventionally, this type of multilayer chip carrier, as shown in FIGS. 4 to 6, has a cavity c for storing a semiconductor element b formed in the center of a carrier body a, and a cavity c on the outer periphery inside the cavity c. A bonding ground f is arranged on the upper surface e of the stepped portion d formed along the length, a plurality of layers of internal electrodes g are provided in the carrier body a, and an external connection terminal i is provided on the outer surface h of the carrier body a. Generally, it consists of a
（考案が解決しようとする問題点）
従来の多層チツプキヤリアは、多層配線を必要
とするボンデイングランドｆを、ボンデイングラ
ンドｆ自体にスルーホールを形成してその下層の
内部電極ｇに接続した場合は、ボンデイングラン
ドｆの表面が荒れる為にボンデイングした際に接
続不良が発生し易いという不都合を有していた。
そこで第５図示の如く多層配線を必要とするボン
デイングランドｆをキヤリア本体ａの内部に引き
込んでからスルーホールｊを介して下層の内部電
極ｇに接続しているが、外部接続用端子ｉとの絶
縁不良が起きやすいために、キヤリア本体ａのキ
ヤビテイｃと外側面間の長さを大きくしなければ
ならないという不都合を有していた。(Problems to be solved by the invention) In the conventional multilayer chip carrier, when the bonding ground f, which requires multilayer wiring, is connected to the internal electrode g of the lower layer by forming a through hole in the bonding ground f itself, Since the surface of the bonding land f becomes rough, there is a problem in that poor connection is likely to occur during bonding.
Therefore, as shown in Figure 5, the bonding ground f, which requires multilayer wiring, is drawn into the inside of the carrier body a and then connected to the lower layer internal electrode g via the through hole j, but the connection with the external connection terminal i is Since insulation failure is likely to occur, the length between the cavity c and the outer surface of the carrier body a must be increased, which is a disadvantage.
本考案は前記不都合を解消した多層チツプキヤ
リアを提供することを目的とする。 The object of the present invention is to provide a multilayer chip carrier that eliminates the above-mentioned disadvantages.
（問題点を解決するための手段）
本考案は、キヤリア本体の中央部に半導体素子
の収納用キヤビテイを形成すると共に該キヤビテ
イ内の外周に沿つて形成された段部の上面にボン
デイングランドを配設し、該キヤリア本体内に複
数層の内部電極を設け、該キヤリア本体の外側面
に外部接続用端子を配設して成る多層チツプキヤ
リアにおいて、該段部の内側に段差面を設けると
共に該段差面に該ボンデイングランドより下層の
内部電極を引き出して引出し電極を形成し、多層
配線を必要とするボンデイングランドを段部の内
壁面に設けた導電部を介して該引出し電極に接続
したことを特徴とする。(Means for Solving the Problems) The present invention forms a cavity for storing a semiconductor element in the center of a carrier body, and arranges a bonding land on the upper surface of a step formed along the outer periphery of the cavity. In a multilayer chip carrier comprising a plurality of layers of internal electrodes provided in the carrier body and external connection terminals provided on the outer surface of the carrier body, a step surface is provided inside the step portion, and a step surface is provided inside the step portion. A lead-out electrode is formed by drawing out an internal electrode in a layer lower than the bonding land on the surface, and the bonding land, which requires multilayer wiring, is connected to the lead-out electrode via a conductive part provided on the inner wall surface of the stepped portion. shall be.
（実施例）
以下、添附図面に従つて本考案の実施例に付き
説明する。(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
図中１はセラミツク製のキヤリア本体を示し、
該キヤリア本体１の中央部に半導体素子２の収納
用キヤビテイ３を形成すると共に該キヤビテイ３
内の外周に沿つて形成された段部４の上面５の全
周にボンデイングランド６を多数配設し、該キヤ
リア本体１内に複数層、図示のものでは３層の内
部電極７を設け、該キヤリア本体１の外側面８に
その上下両端に亘る外部接続用端子９を多数配設
してある。 1 in the figure shows the carrier body made of ceramic.
A cavity 3 for storing the semiconductor element 2 is formed in the center of the carrier body 1.
A large number of bonding lands 6 are disposed all around the upper surface 5 of the stepped portion 4 formed along the inner outer periphery, and a plurality of layers, three layers in the illustrated example, of internal electrodes 7 are provided within the carrier body 1. A large number of external connection terminals 9 are provided on the outer surface 8 of the carrier body 1, extending from both upper and lower ends thereof.
以上の構成は従来の多層チツプキヤリアと特に
異なるとろはないが、本考案の特徴とするところ
に従つて、該段部４の内側に段差面１０を設ける
と共に該段差面１０に該ボンデイングランド６よ
り下層の内部電極７を引き出して引出し電極１１
を形成し、多層配線を必要とするボンデイングラ
ンド６を該段部４の内壁面１２に設けた導電部１
３を介して所望の引出し電極１１に接続した。
尚、図中１４は内部電極７を接続するスルーホー
ルを示す。 Although the above structure is not particularly different from the conventional multilayer chip carrier, according to the features of the present invention, a stepped surface 10 is provided inside the stepped portion 4, and the bonding land 6 is provided on the stepped surface 10. The lower internal electrode 7 is pulled out to form a lead-out electrode 11.
The conductive part 1 has a bonding land 6 formed on the inner wall surface 12 of the stepped part 4 and which requires multilayer wiring.
3 to a desired extraction electrode 11.
Note that 14 in the figure indicates a through hole to which the internal electrode 7 is connected.
本実施例ではボンデイングランド６の１層下の
内部電極７から引出し電極１１を引き出したが、
２層下の内部電極７等、任意の内部電極７から引
き出し電極１１を引き出すことができる。 In this embodiment, the extraction electrode 11 was drawn out from the internal electrode 7 one layer below the bonding land 6.
The extraction electrode 11 can be extracted from any internal electrode 7, such as the internal electrode 7 two layers below.
（考案の効果）
このように、本考案によるときは、ボンデイン
グランドの段部の内側に設けられた段差面上の引
出し電極を利用してボンデイングランドをその下
層の内部電極に接続するようにしたので、キヤリ
ア本体のキヤビテイと外側面との間の長さを大き
くとらなくても外部接続用端子との絶縁不良を生
じないで多層配線のできるコンパクトな多層チツ
プキヤリアを提供できる等の効果を有する。(Effect of the invention) As described above, according to the invention, the bonding land is connected to the internal electrode of the lower layer by using the extraction electrode on the step surface provided inside the step of the bonding land. Therefore, it is possible to provide a compact multilayer chip carrier that allows multilayer wiring without causing poor insulation with external connection terminals without increasing the length between the cavity and the outer surface of the carrier body.
第１図は本考案の１実施例の斜視図、第２図は
第１図の−線截断面図、第３図は第１図の部
分拡大図、第４図は従来例の斜視図、第５図は第
４図の−線截断面図、第６図は第４図の部分
拡大図である。
１……キヤリア本体、３……収納用キヤビテ
イ、４……段部、５……上面、６……ボンデイン
グランド、７……内部電極、８……外側面、９…
…外部接続用端子、１０……段差面、１１……引
出し電極、１２……内壁面、１３……導電部。
FIG. 1 is a perspective view of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line -- in FIG. 1, FIG. 3 is a partially enlarged view of FIG. 1, and FIG. 4 is a perspective view of a conventional example. 5 is a sectional view taken along the line -- in FIG. 4, and FIG. 6 is a partially enlarged view of FIG. 4. DESCRIPTION OF SYMBOLS 1... Carrier main body, 3... Storage cavity, 4... Step part, 5... Top surface, 6... Bonding land, 7... Internal electrode, 8... Outer surface, 9...
... External connection terminal, 10 ... Step surface, 11 ... Extraction electrode, 12 ... Inner wall surface, 13 ... Conductive part.
Claims (1)
ヤビテイを形成すると共に該キヤビテイ内の外周
に沿つて形成された段部の上面にボンデイングラ
ンドを配設し、該キヤリア本体内に複数層の内部
電極を設け、該キヤリア本体の外側面に外部接続
用端子を配設して成る多層チツプキヤリアにおい
て、該段部の内側に段差面を設けると共に該段差
面に該ボンデイングランドより下層の内部電極を
引き出して引出し電極を形成し、多層配線を必要
とするボンデイングランドを段部の内壁面に設け
た導電部を介して該引出し電極に接続したことを
特徴とする多層チツプキヤリア。 A cavity for storing a semiconductor element is formed in the center of the carrier body, and a bonding land is provided on the upper surface of a stepped part formed along the outer periphery of the cavity, and multiple layers of internal electrodes are provided in the carrier body. In a multilayer chip carrier in which external connection terminals are arranged on the outer surface of the carrier body, a stepped surface is provided inside the stepped portion, and internal electrodes in a layer lower than the bonding land are drawn out from the stepped surface. A multilayer chip carrier characterized in that an electrode is formed and a bonding land requiring multilayer wiring is connected to the lead electrode via a conductive part provided on the inner wall surface of the step part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987096416U JPH0452996Y2 (en) | 1987-06-23 | 1987-06-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987096416U JPH0452996Y2 (en) | 1987-06-23 | 1987-06-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6413139U JPS6413139U (en) | 1989-01-24 |
| JPH0452996Y2 true JPH0452996Y2 (en) | 1992-12-14 |
Family
ID=31321319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987096416U Expired JPH0452996Y2 (en) | 1987-06-23 | 1987-06-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0452996Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3718518B2 (en) | 2003-10-03 | 2005-11-24 | 日東電工株式会社 | Photorefractive index modulation polymer, photorefractive index modulation polymer composition, and refractive index control method |
-
1987
- 1987-06-23 JP JP1987096416U patent/JPH0452996Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6413139U (en) | 1989-01-24 |
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