JPH0426899Y2 - - Google Patents
Info
- Publication number
- JPH0426899Y2 JPH0426899Y2 JP806083U JP806083U JPH0426899Y2 JP H0426899 Y2 JPH0426899 Y2 JP H0426899Y2 JP 806083 U JP806083 U JP 806083U JP 806083 U JP806083 U JP 806083U JP H0426899 Y2 JPH0426899 Y2 JP H0426899Y2
- Authority
- JP
- Japan
- Prior art keywords
- zener diode
- bias current
- turned
- supply means
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000001514 detection method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 6
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 4
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
- Power Conversion In General (AREA)
Description
【考案の詳細な説明】
［産業上の利用分野］
本考案は、定電圧電源回路に関するものであ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a constant voltage power supply circuit.
［従来の技術、及び考案が解決しようとする課
題］
従来、定電圧電源回路は第１図に示すように構
成されている。同図において、１は入力電源
（Vi）、２は出力電圧（Vp）Q1は前記入出力１−
２間に直列接続された被制御トランジスタ、R1
は前記入力電源１（Q1のコレクタ）とベース間
に接続された抵抗、D1、及びＣはそれぞれQ1の
ベースと接地間に並列接続されたツエナーダイオ
ードと、前記ツエナーダイオードD1のノイズを
除去するためのコンデンサである。[Prior art and problems to be solved by the invention] Conventionally, a constant voltage power supply circuit has been configured as shown in FIG. In the figure, 1 is the input power supply (V i ), 2 is the output voltage (V p ), and Q 1 is the input/output 1 -
A controlled transistor connected in series between R 2 and R 1
is the resistor connected between the input power supply 1 (collector of Q 1 ) and the base, D 1 and C are the Zener diode connected in parallel between the base of Q 1 and the ground, and the noise of the Zener diode D 1 , respectively. This is a capacitor for removing .
以上の構成において、ツエナーダイオードD1
は一般にツエナーノイズやツエナー電圧の温度特
性などに対して最適値が存在し、これらを考慮し
てツエナーダイオードD1に流すバイアス電流は、
通常2mA〜3mAに設定される。従つてこのバイ
アス電流により抵抗R1の値が決定され、前記抵
抗R1の値をあまり大きくできないので、リツプ
ル除去が不十分であるとともに、電源ON時の出
力電圧の応答特性の高速化は困難である。 In the above configuration, the Zener diode D 1
In general, there is an optimal value for Zener noise and the temperature characteristics of Zener voltage, and taking these into account, the bias current flowing through Zener diode D1 is:
Usually set to 2mA to 3mA. Therefore, the value of the resistor R1 is determined by this bias current, and the value of the resistor R1 cannot be made too large, so ripple removal is insufficient and it is difficult to speed up the response characteristics of the output voltage when the power is turned on. It is.
そこで第２図に示すように、抵抗R1に代えて
デイプレツシヨンタイプのFETQ2を用い、これ
によりツエナーダイオードD1のバイアス電流を
定電流で供給するようにすると、第５図に示すよ
うに前記FETQ2のドレイン−ソース間の電圧が
VA（通常3V程度）以上ではドレイン電流は定電
流特性を示し、交流動作抵抗は数100KΩとなる
ため充分なリツプル除去ができる。 Therefore, as shown in Fig. 2, a depletion type FET Q 2 is used in place of the resistor R 1 , and this supplies the bias current of the Zener diode D 1 as a constant current, as shown in Fig. 5. As shown above, the voltage between the drain and source of FETQ 2 is
Above V A (usually about 3 V), the drain current exhibits constant current characteristics, and the AC operating resistance is several 100KΩ, making it possible to sufficiently remove ripples.
しかしながら、FETQ2のドレイン電流とツエ
ナーダイオードD1のバイアス電流は同一（2mA
〜5mA）のため必要以上に大きくできないので、
第７図に示すように、電源ON時における出力電
圧の応答特性の高速化が困難であつた。 However, the drain current of FETQ 2 and the bias current of Zener diode D 1 are the same (2mA
~5mA), so it cannot be made larger than necessary.
As shown in FIG. 7, it was difficult to increase the response characteristics of the output voltage when the power was turned on.
そこで本考案は上記の点に鑑みて成されたもの
で、簡単な回路構成により、高リツプル除去、及
び出力電圧応答の高速化を可能にした定電圧電源
回路を提供するものである。 The present invention has been developed in view of the above points, and provides a constant voltage power supply circuit that can eliminate high ripples and increase the speed of output voltage response with a simple circuit configuration.
［課題を解決するための手段］
上記課題を解決するために成された本考案は、
第９図に示すごとく、入出力１−２間に直列接続
された被制御トランジスタ３と、前記被制御トラ
ンジスタ３のベースに並列接続されたツエナーダ
イオード４及び前記ツエナーダイオード４のノイ
ズ除去用コンデンサ８と、前記ツエナーダイオー
ド４及びノイズ除去用コンデンサ８と入力１間に
接続され前記ツエナーダイオード４に定電流のバ
イアス電流を供給するバイアス電流供給手段７
と、前記ツエナーダイオード４のON状態を検出
する検出手段５と、前記検出手段５の出力に応じ
て前記バイアス電流供給手段７よりのバイアス電
流を切換える切換手段６とを備え、入力電圧１の
電源ON時に前記バイアス電流供給手段７より大
電流のバイアス電流を流して前記ノイズ除去用コ
ンデンサ８を急速充電され、前記ツエナーダイオ
ード４がON状態になると前記検出手段５にてこ
れを検出し、前記切換手段６により前記バイアス
電流供給手段７より最適バイアス電流を前記ツエ
ナーダイオード４に供給するようにしたことを特
徴とする。[Means for solving the problem] The present invention was made to solve the above problem.
As shown in FIG. 9, a controlled transistor 3 is connected in series between the input and output 1 and 2, a Zener diode 4 is connected in parallel to the base of the controlled transistor 3, and a noise removal capacitor 8 for the Zener diode 4 is connected in parallel to the base of the controlled transistor 3. and bias current supply means 7 connected between the Zener diode 4 and the noise removal capacitor 8 and the input 1 and supplying a constant bias current to the Zener diode 4.
, a detection means 5 for detecting the ON state of the Zener diode 4, and a switching means 6 for switching the bias current from the bias current supply means 7 according to the output of the detection means 5, When ON, a large bias current is passed from the bias current supply means 7 to quickly charge the noise removal capacitor 8, and when the Zener diode 4 is turned ON, the detection means 5 detects this, and the switching is performed. The present invention is characterized in that the means 6 supplies the optimum bias current from the bias current supply means 7 to the Zener diode 4.
［実施例］
以下本考案の実施例を図に基づいて説明する。
第３図において、入出力１−２間に被制御トラン
ジスタQ1が直列接続され、そのベースと接地間
にツエナーダイオードD2と抵抗R4の直列回路と、
コンデンサＣが並列接続されている。また前記被
制御トランジスタQ1のベース（D2のカソード）
とコレクタ（入力１）間にFETQ3が接続され、
そのゲート・ソース間に抵抗R3接続される。さ
らにFETQ3のゲートと接地間に抵抗R2とトラン
ジスタQ5が直列接続され、そのベースはツエナ
ーダイオードD2のアノードと抵抗R4の接続点に
接続される。[Example] Hereinafter, an example of the present invention will be described based on the drawings.
In FIG. 3, a controlled transistor Q 1 is connected in series between input and output 1 and 2, and a series circuit of a Zener diode D 2 and a resistor R 4 is connected between its base and ground.
Capacitor C is connected in parallel. Also the base of the controlled transistor Q1 (cathode of D2 )
FETQ 3 is connected between and the collector (input 1),
A resistor R3 is connected between its gate and source. Further, a resistor R 2 and a transistor Q 5 are connected in series between the gate of FET Q 3 and the ground, and the base thereof is connected to the connection point between the anode of the Zener diode D 2 and the resistor R 4 .
以上の構成において、電源ON時にはツエナー
ダイオードD2及びトランジスタQ5は共にOFF状
態にあり、ツエナー電流供給用FETQ3のゲー
ト・ソース間電圧VGSはVGS＝０となるため、ド
レイン電流IDSSの大電流でコンデンサＣは急速に
充電される。 In the above configuration, when the power is turned on, the Zener diode D 2 and the transistor Q 5 are both in the OFF state, and the gate-source voltage V GS of the Zener current supply FET Q 3 becomes V GS = 0, so the drain current I DSS The capacitor C is rapidly charged by the large current.
次に所定時間経過後にツエナーダイオードD2
がONするとトランジスタQ5がONされ、前記
FETQ3のゲート・ソース間電圧VGSは約
−R3／R2＋R3・VZ
（VZはツエナーダイオードD2のオン時の電圧）
となる。この状態においてFETQ3のドレイン電
流をツエナーダイオードD2の最適バイアス電流
となるように抵抗R2及びR3を設定しておく。そ
こで電源投入後のFETQ3のドレイン電流A及び
出力電圧V0はそれぞれ第８図に示すような特性
となる。すなわち、ツエナーダイオードD2がON
されるまでコンデンサＣは大電流で充電され、ツ
エナーダイオードD2がONされるとツエナーダイ
オードD2の最適バイアス電流を定電流で供給す
ることにより、電源ON時における立上がりの高
速化及び高リツプル除去が実現できるものであ
る。 Next, after a predetermined period of time, the Zener diode D 2
When is turned on, transistor Q5 is turned on, and the above
The gate-source voltage V GS of FETQ 3 is approximately −R 3 /R 2 +R 3・V Z (V Z is the voltage when Zener diode D 2 is on)
becomes. In this state, resistors R 2 and R 3 are set so that the drain current of FETQ 3 becomes the optimum bias current of Zener diode D 2 . Therefore, after the power is turned on, the drain current A and output voltage V 0 of FETQ 3 have characteristics as shown in FIG. 8, respectively. That is, Zener diode D 2 is ON
The capacitor C is charged with a large current until the Zener diode D2 is turned on, and by supplying the optimum bias current of the Zener diode D2 with a constant current, it is possible to speed up the rise time and eliminate high ripples when the power is turned on. can be realized.
また、第４図に示すように、ゲート・ソース間
電圧VGSが０のときのドレイン電流IDSSがツエナー
ダイオードD2の最適バイアス電流となるFETQ2
と、IDSSが充分に大きくかつVGS＝−VZのとき
OFF状態となるFETQ4を設けることにより、電
源ON時にはツエナーダイオードD2及びトランジ
スタQ5はOFFであり、FETQ4がVGS＝０のとき
FETQ2，Q4のIDSSでコンデンサＣは急速に充電さ
れる。ツエナーダイオードD2がONするとトラン
ジスタQ5はONされ、FETQ4のVGSは−VZと略等
しくなり、FETQ4はOFFとなる。そしてツエナ
ーダイオードD2にはFETQ2により最適バイアス
電流が供給される。上記実施例における入力電源
投入後の特性を第８図に示す。 Furthermore, as shown in FIG. 4, the drain current I DSS when the gate-source voltage V GS is 0 is the optimum bias current of the Zener diode D 2 .
and when I DSS is sufficiently large and V GS = −V Z
By providing FETQ 4 that is in the OFF state, Zener diode D 2 and transistor Q 5 are OFF when the power is turned on, and when FETQ 4 is V GS = 0.
Capacitor C is rapidly charged by I DSS of FETQ 2 and Q 4 . When the Zener diode D2 is turned on, the transistor Q5 is turned on, VGS of FETQ4 becomes approximately equal to -VZ , and FETQ4 is turned off. The optimum bias current is then supplied to the Zener diode D2 by FETQ2 . FIG. 8 shows the characteristics of the above embodiment after the input power is turned on.
尚、上記各実施例では正極性の定電圧電源回路
について説明したが、負極性の定電圧電源回路に
ついても同様の効果を奏する。また、上記実施例
ではツエナーダイオードD2がONしたことを検出
するのにNPN型トランジスタを使用したが、他
の構成を用いてもよい。さらにFETのゲート・
ソース間電圧VGSを切換える回路も他の構成を用
いてもよい。 In each of the above embodiments, a positive polarity constant voltage power supply circuit has been described, but a negative polarity constant voltage power supply circuit also has the same effect. Further, in the above embodiment, an NPN transistor is used to detect that the Zener diode D2 is turned on, but other configurations may be used. In addition, the FET gate
Other configurations may also be used for the circuit that switches the source-to-source voltage VGS .
［効果］
以上のように、本考案によれば高リツプル除去
でかつ電源の立上がりが高速な定電圧電源回路を
簡単な回路で構成できる。[Effects] As described above, according to the present invention, a constant voltage power supply circuit with high ripple rejection and high power supply startup speed can be constructed with a simple circuit.
第１図、第２図は従来の定電圧電源回路を示す
図、第３図、第４図はそれぞれ本考案による定電
圧電源回路例を示す図、第５図はFETのドレイ
ン電流とドレイン・ソース間電圧の関係を示す
図、第６図はドレイン電流とゲート・ソース間電
圧との関係を示す図、第７図は従来の定電圧電源
回路における出力応答特性を示す図、第８図は本
考案による出力応答特性を示す図、第９図は本考
案の構成を示す図である。
１……入力電圧、２……出力電圧、３……被制
御トランジスタ、４……ツエナーダイオード、５
……検出手段、６……切換手段、７……バイアス
電流供給手段（デイプレツシヨンタイプFET）、
８……コンデンサ。
1 and 2 show conventional constant voltage power supply circuits, FIGS. 3 and 4 show examples of constant voltage power supply circuits according to the present invention, and FIG. 5 shows drain current and drain current of FET. Figure 6 is a diagram showing the relationship between source voltage, Figure 6 is a diagram showing the relationship between drain current and gate-source voltage, Figure 7 is a diagram showing the output response characteristics of a conventional constant voltage power supply circuit, and Figure 8 is a diagram showing the relationship between the drain current and gate-source voltage. FIG. 9 is a diagram showing the output response characteristics according to the present invention, and is a diagram showing the configuration of the present invention. 1... Input voltage, 2... Output voltage, 3... Controlled transistor, 4... Zener diode, 5
...Detection means, 6...Switching means, 7...Bias current supply means (depression type FET),
8... Capacitor.
Claims (1)
と、 前記被制御トランジスタのベースに並列接続さ
れたツエナーダイオード及び前記ツエナーダイオ
ードのノイズ除去用コンデンサと、 前記ツエナーダイオード及びノイズ除去用コン
デンサと入力間に接続され前記ツエナーダイオー
ドに定電流のバイアス電流を供給するバイアス電
流供給手段と、 前記ツエナーダイオードのON状態を検出する
検出手段と、 前記検出手段の出力に応じて前記バイアス電流
供給手段よりのバイアス電流を切換える切換手段
とを備え。 入力電圧の電源ON時に前記バイアス電流供給
手段より大電流のバイアス電流を流して前記ノイ
ズ除去用コンデンサを急速充電させ、前記ツエナ
ーダイオードがON状態になると前記検出手段に
てこれを検出し、前記切換手段により前記バイア
ス電流供給手段より最適バイアス電流を前記ツエ
ナーダイオードに供給するようにしたことを特徴
とする定電圧電源回路。[Claims for Utility Model Registration] A controlled transistor connected in series between input and output, a Zener diode connected in parallel to the base of the controlled transistor, and a noise removal capacitor for the Zener diode, and the Zener diode and the noise. bias current supply means connected between a removal capacitor and an input and supplying a constant bias current to the Zener diode; a detection means for detecting an ON state of the Zener diode; and a bias current supply means for supplying a constant bias current to the Zener diode; It is equipped with a switching means for switching the bias current from the current supply means. When the input voltage power supply is turned on, a large bias current is caused to flow from the bias current supply means to quickly charge the noise removal capacitor, and when the Zener diode is turned on, this is detected by the detection means and the switching is performed. A constant voltage power supply circuit characterized in that the bias current supply means supplies an optimum bias current to the Zener diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP806083U JPS59113813U (en) | 1983-01-24 | 1983-01-24 | Constant voltage power supply circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP806083U JPS59113813U (en) | 1983-01-24 | 1983-01-24 | Constant voltage power supply circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59113813U JPS59113813U (en) | 1984-08-01 |
| JPH0426899Y2 true JPH0426899Y2 (en) | 1992-06-29 |
Family
ID=30139567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP806083U Granted JPS59113813U (en) | 1983-01-24 | 1983-01-24 | Constant voltage power supply circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59113813U (en) |
-
1983
- 1983-01-24 JP JP806083U patent/JPS59113813U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59113813U (en) | 1984-08-01 |
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