JPH04271432A - Operand designating method and central arithmetic processing unit using this method - Google Patents

Abstract

PURPOSE:To realize the operand method where data of an operand and a number to be operated can be held to especially execute the operation between memory data at a high speed and the instruction word length is short. CONSTITUTION:In the operand designating method of a CPU where only operation data and data to be operated are designated as operands, first memory data stored in a first memory is designated as first operand data, and second memory data stored in a second memory is designated as second operand data, and the operation between first and second operand data is executed, and data of the operation result is stored in a specific register provided in this CPU.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of specifying operands for a central processing unit (hereinafter referred to as CPU) and a central processing unit using the calculation method.

0002

2. Description of the Related Art There are three types of operand data handled by a CPU: register data, immediate data, and memory data. Register data refers to data stored in one or more registers that the CPU has as internal hardware, and immediate data refers to immediate values written in a program. Memory data is CP
The data to be stored in the memory specified by U, C
A PU generally has an addressing mode that enables efficient and high-speed access to a wide memory space. Furthermore, in the CPU instruction system, there are multiple methods of specifying operands depending on the architecture. Addition instruction (
The above specification method will be explained below using ADD) as an example. a. 3-operand method C ← A + BA, B,
C indicates an operand, and in the instruction, A is the operand and is the data stored in the first operand, and B is the operand and is the data stored in the second operand.
and the added data that is the result of the addition is stored in the third operand. In this way, three operands are independently specified for each data readout and storage destination. b. 2-operand method A ← A +
B or in the B←A+B command,
Two operands A and B are specified, and the result of the operation is stored in either of the two operands, updating the data stored before the operation. c. 1-operand method Acc ← Acc +
A or A←Acc+A In the instruction, one operand A is specified, the operation is performed on the data stored in the accumulator indicated by Acc, which is a special register dedicated for operation, and the operation result is transferred to the accumulator or Store in the specified operand.

0003

[Problems to be Solved by the Invention] Considering the problems of each of the above-mentioned methods a to c, the three-operand method shown in a has the highest degree of freedom in terms of selectivity because three operands can be specified independently. is high. Furthermore, when the instruction is addition, there is a feature that the operand and operand, which are the first operand data and second operand data, are not updated after the operation. However, specifying three operands in an instruction has the disadvantage that the length of the instruction word becomes long. Therefore, as a way to avoid this drawback, Motorola's MC8
Although it is stated in the user manual of the 8100, even with the 3-operand system adopted by the CPU, as in the RISC architecture shown below, operand data that can be used is limited to registers rather than memory, and operand selectivity is expanded. There are methods to prevent the instruction word length from increasing. a'RISC 3-operand system R3←R1+R2 Here, R1, R2, R3
is register data.

On the other hand, in the case of the one-operand method shown in c,
Although the degree of freedom is low in terms of operand selectivity, it has the advantage of shortening the instruction word length to be allocated in an instruction. However, in c, the operation target is always the data stored in the accumulator, so the registers that can be operated on are limited, and it is necessary to prepare by transferring the operation data to the accumulator each time the operation is performed, and after the operation, transfer the result data from the accumulator. However, it has the disadvantage of increasing the program size and the number of execution cycles. Therefore, the two-operand method shown in b, which is an intermediate method between the two, has relatively high operand selectivity and short instruction word length, so the two-operand method is often used in CPUs that have registers that can perform multiple operations. ing. However, in the two-operand method, as mentioned above, the data stored in one of the operands is updated after the operation, so if you want to keep the operands and operands unchanged, it is better than the three-operand method. However, there is a problem in that it is necessary to add a program for saving data. In addition, as mentioned above, operand data includes register data, immediate data, and memory data, so a CP that has multiple registers that can be operated on.
If the combinations of operations on each of the above data using the two-operand method of U are classified based on the addition instruction, the following d or i
become that way.

[0005]d. R1 ← R1 + R
2e. R1 ← R1 + M1f.
R1 ← R1 + IM1g. M1
← M1 + R1h. M1 ← M1
+ IM1i. M1 ← M1 +
M2

[0006] These show the following. That is, the above d indicates adding the data R1 stored in the register R1 and the data R2 stored in the register R2, and storing the addition result in the register R1, and the above e
indicates that the data R1 stored in the register R1 and the memory data M1 stored in the memory M1 are added, and the addition result is stored in the register R1, and the above f indicates that the data R1 stored in the register R1 and the immediate IM1
and the immediate data IM1 stored in
The above g indicates that the addition result is stored in the register R1, and the above g indicates that the memory data M1 stored in the memory M1 and the data R1 stored in the register R1 are added, and the addition result is stored in the memory M1. The above h indicates adding the memory data M1 stored in the memory M1 and the immediate data IM1 stored in the immediate IM1, and storing the addition result in the memory M1. Add the memory data M1 stored in the memory M2 and the memory data M2 stored in the memory M2,
This shows that the addition result is stored in the memory M1.

[0007] Now, consider the proposition M3←M1+M2. That is, this proposition states that memory data M1 stored in memory M1 and memory data M2 stored in memory M2
The proposition is to add the results and store the result in the memory M2, and adds a condition that the memory data M1 and M2 must retain the data before the calculation even after the calculation. In this case, as described above, a CPU that uses a three-operand system completes the process with one instruction, but a conventional CPU that uses a two-operand system requires a plurality of program steps as shown below.

j. MOV R1, M1 … R1
←M1k. ADD R1, M2...
R1←R1+M2m. MOV M3, R1
… M3←R1

That is, the instruction shown in j is an instruction to transfer the memory data M1 stored in the memory M1 to the register R1, and the instruction shown in k is an instruction to transfer the data stored in the register R1, that is, the memory data M1 and the memory data M2 stored in the memory M2. This is an instruction to add the memory data M2 and the addition result to the register R1, and the instruction shown in m adds the data stored in the register R1, that is, the data obtained by adding the memory data M1 and M2, to the memory M3. This is a command to transfer. In this way, if we try to execute the above proposition with two operands, it will take three instructions.

The present invention was made in order to solve the above-mentioned problems, and it is possible to hold data of operands and operands, and in particular, to execute operations between memory data at high speed.
It is an object of the present invention to provide a CPU operand specification method that has a short instruction word length, and a CPU that uses the method.

[0011]

[Means for Solving the Problems and Their Effects] The present invention provides a C
In the PU two-operand specification method, the first memory data stored in the first memory is specified as the first operand data, the second memory data stored in the second memory is specified as the second operand data, and the first and second operand data, and stores the result data of the operation in a specific register provided within the CPU.

By adopting such a method, the data stored in the first and second memories will not be rewritten even though it is a two-operand method, and the instruction word length will be reduced compared to the three-operand method. becomes shorter.

Further, the present invention provides a central processing unit that adopts a two-operand specification method for a central processing unit in which only operation data and operand data are specified by operands, and a central processing unit that is provided in the central processing unit and that specifies the operation data. an internal register unit that stores and sends the operation result data of and the operand data; a control unit that generates a control signal for storing the operation result data in the internal register unit;
It is characterized by having the following.

The internal register section stores operation result data based on the operation data and the operand data, and sends the stored data to a memory other than the memory that stores the operation data and the operation data.

[0015]

[Example] The operand system of the CPU in this example employs a two-operand system, and its operation is described above.
The following will explain the proposition ←M1+M2 as an example. In the two-operand system in the CPU of this embodiment, the following n, p
The above proposition is completed with the following two instructions. n. ADD M1, M2...
Rs ← M1+M2 p. M.O.V.
M3, R1 … M3 ← R
s

That is, the instruction indicated by n adds memory data M1 stored in memory M1 and memory data M2 stored in memory M2, and stores the resulting data in an internal register Rs within the CPU. The instruction indicated by p stores the result data stored in the register Rs in the memory M3. By using the CPU's internal registers in this way, in the conventional two-operand system, it takes three to complete a proposition.
What used to require one instruction can be completed with two instructions, and inter-memory operations can be executed with two-thirds the number of instructions compared to the conventional method, allowing for reduction in program size and high-speed operations.

[0017] Furthermore, in terms of the format of the instructions,
As shown in FIG. 1, it consists of a bit Ln that identifies instructions such as ADD and MOV, and bit groups mn1 and mn2 that specify memory operands. The format is the same as in the CPU, and the length of the instruction word does not become longer. Incidentally, as shown in FIG. 2(b), the instruction word length in the two-operand system of this embodiment is naturally shorter than the format in the three-operand system CPU.

Note that even in the conventional two-operand system, it is possible to execute the above proposition with two instructions according to the following instructions q and r. q. MOV M3, M1 … M3
←M1r. ADD M3, M2...
The command shown in M3←M3+M2q is a command to store memory data M1 stored in memory M1 into memory M3, and the command shown in r is a command to store data stored in memory M3, that is, memory data M1 and memory data M2. memory data M2 and the resulting data is added to memory M2.
This is an instruction to store in 3. However, in this case, although the number of instructions is the same as in the present embodiment, the so-called number of cycles required to execute the instructions is greater than in the present embodiment, and the calculation processing time becomes slower. That is, the instruction q has two functions: reading from memory M1 and writing to memory M3.
In the instruction r, memory M2 and memory M3
It requires three steps: reading data from the memory M3 and writing data to the memory M3, and a total of five steps are required for instructions q and r. However, instruction fetch and internal address cycles are excluded. On the other hand, in the two-operand system of this embodiment, since register Rs is an internal register of the CPU in instruction n, writing to register Rs does not require the number of steps, and reading data from memory M1 and memory M2 does not require a number of steps. Two steps are required, and instruction p requires one step to write data to memory M2. Therefore, instructions n, p
It only takes 3 steps in total.

[0019] Also, in the three-operand system, the instruction s
Compared to R1←M1+M2, the number of steps mentioned above is one step shorter with instruction s, but as mentioned above, the instruction word length is shorter with the two-operand method of this embodiment, so the calculation processing time is shorter than that of this embodiment. The example-based method allows faster calculations.

In order to execute the two-operand method according to this embodiment, the above-mentioned register Rs may be newly provided in the CPU, or a predetermined portion of an existing internal register in the CPU may be used. Also, by providing a resistor Rs, C
It is necessary to send data related to the addition and modification of control codes from the control unit in the PU, but as mentioned above, by using the existing internal registers of the CPU, the burden on the hardware can be kept to a minimum. can.

[0021]

As described in detail above, according to the present invention, by storing the operation result data of operand data in a specific internal register of the CPU, operations using operand data can be performed even though the two-operand method is used. Operations can be performed without rewriting data or operand data,
The instruction word length can be made shorter than the three-operand method. In addition, by using the internal registers of the CPU, the operation data and operand data can be directly operated, which reduces the number of instructions compared to the conventional two-operand method, which executes operations without rewriting the operation data or operand data. It can be reduced. Therefore, the CP of the conventional two-operand method
Compared to U, calculation processing can be made faster.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an instruction format in the operand method of the present invention.

FIG. 2 is a diagram showing instruction formats in conventional two-operand systems and three-operand systems.

[Explanation of symbols]

none

Claims (2)

[Claims] Claim 1. An operand specification method for a central processing unit in which only operation data and operand data are specified by operands, wherein first memory data stored in a first memory is specified as first operand data, and first memory data stored in a first memory is specified as second operand data. Specifying second memory data stored in a second memory as data, executing an operation using first and second operand data, and storing result data from the operation in a specific register provided in the central processing unit. A method for specifying operands for a central processing unit, characterized by: 2. In a central processing unit that adopts a two-operand specification method in which only operation data and operand data are specified by operands, a central processing unit is provided within the central processing unit that performs an operation on the operation data and the operand data. A two-operand specification method is adopted, which is characterized by comprising an internal register section that stores and sends result data, and a control section that generates a control signal for storing the operation result data in the internal register section. Central processing unit.