JPS61190648A - Inter-memory data transfer control circuit - Google Patents

Abstract

PURPOSE:To perform the processing in a high speed by decoding the extended bit output of a program memory to select one of two memories and executing a specific program by a CPU to transfer data. CONSTITUTION:When data of memories 2, 3, and 4 are transferred by a CPU1, a program memory 6 is constituted with an extended bit 62 including memory selecting information and a command, and the command 61 is connected to the CPU1, and the CPU1 supplies the bit 62 to a decoder 7, and the output is applied to permission inputs of memories 2, 3, and 4. Data to be set to the bit 62 is inverted, and the command 61 in the address which is a command of the CPU1 is executed, and for example, '0' of the bit 62 is outputted to read data of the memory 2, and the command in the same address is executed, and '1' of the bit 62 is outputted to write data in the memory 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a control circuit for transferring data in a first memory belonging to the same address space to a memory M2 by a CPU.

(b) Prior art and problems Generally, a CPU cannot access two or more memory cells at one address at the same time, so additional circuits such as a memory mapping circuit and a memory bank switching circuit are provided externally. Perform some address expansion. By connecting some memory to this and changing the settings of the additional circuit, you can create a memo! 'We have adopted a method of switching.

However, in such data transfer between different memories,
As shown in the following example, this method requires complicated handling and has the disadvantage that the transfer speed is significantly slower than transfer within the same memory.

The conventional circuit will be explained below with reference to FIG.

In FIG. 3, 1 is a first memory for the CPU 12, 3 is a second memory, and 5 is an address expansion circuit.

Whether a certain address belongs to memory 2 or memory 3 is determined by a control bit on address expansion circuit 5.

Therefore, the contents of the same address are stored in memory 2 and memory 3.
When copying between data, it is necessary to first read one, change the control bits, write to the other, and then invert again to restore the data, repeating this operation for the number of data.

Next, the flow chart of FIG. 3 is shown in FIG.

In step 11 of FIG. 4, the CPUI reads the memory 2. That is, memory selection information set in advance is supplied to each memory as an address, and as a result, memory 2 is selected and outputs data.

In step 12, the address extension circuit 5 is
Rewrite the address from the CPUI to memory 3.

In step 13, the CPUI data is written into the memory 3.

In step 14, the address of the address expansion circuit 5 is returned from the memory 3 to the memory 2.

In the conventional circuits as shown in FIGS. 3 and 4, extra time is required for changing the address expansion circuit 5, so when the address range becomes wider, there is a problem that the practical allowable time is exceeded.

(c) Purpose of the Invention The present invention employs a program memory and a decoder having extension bits as a means of data transfer between two or more types of memories in the same address space, and uses the extension bits to alternate when reading or writing by the CPU. The purpose of the present invention is to create a program that selects a memory at different times, and to be able to process transfers between the memories at high speed.

(d) Means for Solving the Problems The reason why transfer takes time in the conventional technique as shown in FIG. 3 is because memory selection is performed using extended addresses.

The present invention is characterized in that memory selection information is included in the program.

Next, FIG. 1 shows a diagram of the basic configuration of this invention.

In FIG. 1, 6 is a program memory, and 7 is a decoder.

The memory selection information is stored in an extension bit 82 that extends the word length of the program memory 6. Then, each time the CPUI retrieves an instruction 61 from the program memory 6, an extension bit 62 is supplied to the decoder 7.

As a result, the decoder 7 adds each decode output to the permission inputs of the memory 2, memory 3, and memory 4, and alternately switches between arbitrary memories.

(e) Examples of the invention A configuration diagram of an embodiment according to the present invention is shown in FIG.

FIG. 2 illustrates a case where the extension bit 62 in FIG. 1 is one bit.

Since the extension bit 62 is 1 bit, the decoder 7 in FIG. 1 is implemented by the inverter 8 in FIG.

Although the inverter 8 is connected to the memory 2 in FIG. 2, the inverter 8 may be connected between the memories 3.

In this case, in order to get the same behavior, you need an extension.

Invert the data set in Toro 2.

Next, a configuration diagram of the program memory 6 is shown in FIG.
``61 in FIG. 5 is an instruction, and 62 is an extension bit.

Instructions 61 are directly connected to the CPUI and do not include information about which memory to access.

The expansion and buttons 82 are configured, for example, as rlJ and rOJ, with "0" selecting memory 2, "1" selecting memory 3, and so on.

Next, the flowchart of FIG. 2 is shown in FIG.

At step 21 in FIG. 6, the expansion bit 62 of the program memory θ is set by a command from the CPU 1. In step 22, the CPUI retrieves and executes an instruction 61 to read data from memory at a certain address, and at the same time,
“0” of the extension bit 61 is output to the inverter 8. As a result, memory 2 is selected and the data in memory 2 is transferred to the CPU.
It is read into I.

Similarly, in step 23, the instruction 61 to write to the memory at the same address as in step 22 is executed, and at the same time,
“1” of the extension bit 82 is output to the inverter 8. As a result, memory 3 is selected and CPUI data is written to memory 3.

By repeating steps 21 to 24,
7-data in an arbitrary address range of memory 3 can be transferred to memory 2.

As is clear from a comparison between FIG. 4 and FIG. 6, in FIG. 6 there are no steps 12 and 14 in FIG. 4, so the transfer time can be increased accordingly.

(f) Effects of the Invention According to this invention, since the memory switching information is provided in the transfer program itself rather than in the address expansion circuit,
There is no need to update memory switching information during the data transfer process between memories, and processing can be performed at a correspondingly high speed.

Normally step 12.14 requires more than twice the execution time of step 22.23, so the overall transfer time is reduced to 1/3.
It can be:

[Brief explanation of the drawing]

1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram illustrating an embodiment of the invention, FIG. 3 is a conventional diagram, FIG. 4 is a flowchart of FIG. 2, and FIG. 5 is a program memory 6. FIG. 6 is a flowchart of FIG. 1. 1... CPU, 2... First memory,
3...Second memory, 4...Third memory, 5...Address extension circuit, 8...
・Program memory, 7... Decoder, 8...
...Inverter. Agent Patent Attorney Kinji Omata Figure 1 Figure 2 Inverter Figure 3 Figure 4

Claims (1)

[Scope of Claims] 1. A control circuit for transferring data of a first memory belonging to the same address space to a second memory by a CPU, comprising: a program memory having an extension bit; memory or a decoder for selecting one of the second memory, and the CPU executes a program in which an extension bit is set in advance so that different memories are permitted when reading and writing the memory. A data transfer control circuit between memories, characterized in that the circuit transfers data.