JPH04273334A - Data processing system - Google Patents

Abstract

PURPOSE:To assure the bit of the read data and at the same time to justify the updated read data. CONSTITUTION:A CPU 1 outputs a read instruction signal 25 and reads the data and an error detection/correction code out of the read address of a memory part 4. If a detected bit error of the data is uncorrectable, a detection part 71 informs the CPU 1 of this fact with impression of an error signal 75. If the bit error is correctable, a correction part 72 corrects the relevant bit area of the data with the error detection/correction code and sends the data to a system bus via a 4th control part 50. Then a code destroying part 60 reads out an inputted special read instruction executing signal 35 with an instruction of the part 50 and then inverts and destroys the error detection/correction code into the read data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data processing systems, and more particularly to data processing systems having control using error detection and correction codes.

0002

2. Description of the Related Art In recent years, as computers have become more widespread, information processing devices including computers are required to have high reliability. On the other hand, as the hardware of information processing devices tends to become more complex and larger, the rate of device failure is increasing. In particular, there are cases in which data fraud resulting from undetected faulty parts causes system failures, and there is a need to improve failure detection rates in order to prevent this.

In conventional data processing systems, failure detection circuits for guaranteeing data during memory access are either circuits that add parity to data and detect errors; It has a circuit that adds a correction code and stores it in the storage unit, and when reading the data, detects a data error using the error detection and correction code, and corrects the error location in the case of a correctable error. In an example of a conventional data processing system, Figure 3
As shown in FIG.
300 (referred to as "U") are connected by a system bus 400, and when the execution instruction is a memory write, the CPU 300 specifies the write address and data to be stored in the RAM 100, and sends a write instruction signal to the MMU 200. and a control unit 320 that sends out a read address designation and a read instruction signal and receives data from the MMU 200 via the system bus when the execution command is a memory read. In the MMU 200, an error detection and correction code is added to the write data coming from the control unit 310, and the RA
Control unit 210 to store at specified address of M100
and RAM1 according to the address specified by the control unit 320.
A control unit 220 that reads data from 00, a detection unit 230 that simultaneously reads out the error detection and correction code of the address corresponding to the read data and detects a bit error in the read data, and a correction unit that corrects the data in the case of a correctable error. It had a section 240.

0004

In the data processing system described above, data bits are guaranteed when read, but it is difficult to guarantee the validity of written data. In FIG. 3, correct data and a corresponding error detection and correction code have already been stored at a specific address in the RAM 100, and the stored data is data that is read out only once and is not used again. When writing is performed and the specified address is the specific address and the operation is intended to update the stored data, the write instruction signal of the control unit 310 of the CPU 300 is not transmitted to the control unit 210 of the MMU 200 due to an intermittent failure. If this occurs, the data for the specific address in the RAM 100 will not be updated to write data and no error will be detected. Next, when the execution command is a memory read and the data is read from the specific address, the data before update is read along with the corresponding error detection and correction code;
There was a problem that errors were not detected because the data was correct. Furthermore, there is a problem in that a secondary failure occurs inside or outside the data processing system until a logical contradiction occurs in the use of the data before the update.

[0005]

[Means for Solving the Problems] The data processing system of the present invention includes a central processing unit that executes operations and instructions, and a memory control unit that includes a storage unit that can read and write data at arbitrary addresses. In a data processing system connected by a system bus for transfer, a central processing unit has a central processing unit that instructs a memory control unit to write data and sends an address and write data onto the system bus. 1
a second control unit that instructs the memory control unit to read information from the central processing unit, specifies a read address, and receives read data on the system bus; a special read command control unit that outputs a special read command that instructs a one-time read operation for data; and a signal that notifies the memory control unit that the read operation of the special read command is to be executed; and a memory control unit. The third control unit receives write data sent onto the system bus by writing from the first control unit and writes it to a designated address of the storage unit, and the second control unit a fourth control unit that reads data from a designated address of the storage unit by reading from the storage unit; an addition unit that adds an error detection and correction code to the written data; and a fourth control unit that adds an error detection and correction code to the written data; a detection unit that detects fraudulent data using an error detection and correction code corresponding to the read data, and outputs a signal to notify a central processing unit when the fraudulent data cannot be corrected by the error detection and correction code; A code destruction unit that receives a signal indicating that a read operation is to be executed by a special read command and destroys an error detection and correction code for the read data after the read operation is completed; and a code destruction unit that destroys the error detection and correction code for the read data, and the incorrect data can be corrected by the error detection and correction code. and a correction unit that sends data with corrected incorrect portions onto the system bus when .

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The CPU 1 executes calculations and instructions, and sends a write instruction signal 15 to the MMU 2 and an address to store write data on the system bus 3 by a memory write command, and a first control unit 10 which sends a write instruction signal 15 to the MMU 2 and an address to store write data on the system bus 3 by a memory read command. A control unit 20 that sends a read instruction signal 25 and a read address onto the system bus 3 to the MMU 2 and receives the read data, and a control unit 20 that recognizes the case of a special read command among memory read commands and sends a message to that effect to the MMU 2. It has a special read control section 30 that sends out a special read command execution signal 35 to be transmitted.

The MMU 2 has a third control unit 40 which inputs the write instruction signal 15, receives write data on the system bus, and writes the data to a specified address of the readable and writable storage unit 4, and a third control unit 40 which receives the write instruction signal 15 and writes the data to a specified address of the readable and writable storage unit 4. The write data is input to the storage unit 4, an error detection correction code (hereinafter referred to as "ECC") is generated, and the data is stored in the storage unit 4.
an addition section 70 that receives the read instruction signal 25 and reads out the data and ECC stored at the designated read address from the storage section 4 and sends the data onto the system bus. Section 50 and
A detecting unit 71 receives the read data and ECC described above, detects a bit error in the read data, and if it cannot be corrected, notifies it by an error signal 75, and if it is correctable, corrects the error bit location using the ECC. A correction unit 72 sends the output to the system bus via the control unit 50 of No. 4, and a special read command execution signal 35 when there is a read instruction by the special read command is input, and a read operation is performed under the instruction of the control unit 50. It has a code destruction unit 60 that inverts and destroys the ECC corresponding to the read data after completion.

FIG. 2 is a detailed block diagram showing the configuration of this embodiment. The CPU 501 corresponds to the CPU 1 in FIG.
In the CPU 501, an IR is used to execute instructions stored in an instruction register (hereinafter referred to as "IR") 510.
The instruction code 511 corresponding to the upper byte of 510 is decoded by a decoder (hereinafter referred to as "DEC") 520, and if it is a read command, it is notified to the read control unit (hereinafter referred to as "RCNT") 540, or if it is a write command, it is written. Control unit (hereinafter referred to as “WCNT”) 5
50 to that effect, and the address/data control unit (hereinafter referred to as "
AD/DT CONT) 530, and when it is a special read command among the read commands, a signal 561 indicates that fact.

In contrast to FIG. 1, the signal 561 in FIG.
RCNT540/WCNT550 in Fig. 2 of signal 35
・AD/DC CONT530 is each control unit 1
0. Has the function of the control unit 20.

The MMU 502 in FIG. 2 corresponds to the MMU 2 in FIG. 1, and the memory element (hereinafter referred to as "ERAM") 5 in FIG.
Reference numeral 06 denotes a readable and writable memory for storing ECC and data, and the ECC storage section corresponds to the storage section 4 and the code destruction section 60 in FIG.

[0012] The operation when executing the above-mentioned write command is as follows:
/DT CONT 530 sends a write request signal (hereinafter referred to as "RQE") 533, and the write address and write data are sent to address bus 503 and data bus 504, and address decode (hereinafter referred to as "ADD") is sent to address bus 503 and data bus 504.
EC") 570 decodes the address from the address bus 503 at the timing of RQE 533 and transmits a write instruction to a read/write control unit (hereinafter referred to as "MCNT") 590. At the time of writing, the ECC control unit (hereinafter referred to as "ECCC") 580
An ECC is created from the write data on 4 and stored at the write address via an ECC register (hereinafter referred to as "ECCR") 585 and data bus 504. The operation when executing the above read command is AD/DT CONT
The read address that sent the read request signal RQE533 from 530 is ADDE via the address bus 503.
The C570 decodes the address at the timing of the RQE533 and transmits a read instruction to the MCNT590. M.C.
The NT 590 instructs to send data and the corresponding ECC from the specified address of the ERAM 506 onto the data bus.

The ECCC 580 takes in data and ECC, checks for bit errors in the data, and when an uncorrectable error occurs, notifies the CPU 501 of an error signal 531.
If the error is correctable, correct the error bit and execute ECCR.
585 onto the data bus. When the signal 561 at the end of reading indicates a special read command, the ECC corresponding to the read data stored in the ERAM is inverted and destroyed. Next, when a read command is executed and the read address is the same as the read address, an uncorrectable error is detected in the ECCC 580 because the corresponding ECC has already been destroyed.

[0014]

As described above, the present invention provides a system for processing data stored in a memory and controlled by an error detection and correction code, by providing a special read command and an error detection and correction code read and destroy unit. In addition to guaranteeing the bits of the read data, the read data is guaranteed to be updated data and the written data can be justified, and the data processing system to which the present invention is applied can prevent failures due to the use of unupdated data. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

[Figure 2] Detailed block diagram showing the configuration of this embodiment

FIG. 3 is a block diagram showing the configuration of an example of a data processing system according to conventional technology.

[Explanation of symbols]

1 Central processing unit (CPU) 2 Memory control unit (MMU) 3 System bus 4 Storage unit 10 First control unit 15 Write instruction signal 20 Second control unit 25 Read instruction signal 30 Special read command control unit 35 Special read command Execution signal 40 Third control section 50 Fourth control section 60 Code destruction section 70 Addition section 71 Detection section 72 Correction section 100 Storage section 200 MMU 300 CPU 210, 220 Control section 230 Detection section 240 Correction section 250 Addition section 310, 320 Control unit 400 System bus 410 Error detection signal

Claims (1)

[Claims] 1. A data processing system in which a central processing unit that executes operations and instructions and a memory control unit that includes a storage unit that can read and write data at arbitrary addresses are connected by a system bus that transfers addresses and data. In the central processing unit, the central processing unit includes a first control unit that instructs the memory control unit to write data from the central processing unit and sends an address and write data onto the system bus; A second controller that instructs the memory control unit to read data, specifies a read address, and receives read data on the system bus.
a control unit, a special read command that instructs a one-time read operation for data written at an arbitrary address, and a signal that informs the memory control unit that the read operation of the special read command is to be executed. and a memory control unit that receives write data sent onto the system bus by writing from the first control unit and writes it to a specified address of the storage unit. a third control section; a fourth control section that reads data from a designated address of the storage section by reading from the second control section; and an addition section that adds an error detection and correction code to the written data; When reading data from the storage unit according to the read instruction, invalid data is detected using an error detection and correction code corresponding to the read data, and if any of the invalid data cannot be corrected using the error detection and correction code, a central message is sent to that effect. a detection unit that outputs a signal to inform the processing device; and a code destruction unit that receives a signal indicating that a read operation is to be executed by the special read command and destroys an error detection and correction code for the read data after the read operation is completed. , a correction unit that sends data with corrected portions of the invalid data onto a system bus when the invalid data can be corrected by an error detection and correction code.