JPH0353358A - Memory circuit - Google Patents

Abstract

PURPOSE:To deal with even a fixed fault by writing again the write data into a microprogram with the plus and the minus of the data inverted to each other at occurrence of a fault and reading out the read data with its plus and minus converted to each other in a reading state. CONSTITUTION:It is supposed that such a fault occurs in a certain address in a memory 20 that breaks fixedly the 2nd lower bit of the data '1011' and turns this data into '1001'. Thus the fault is detected by a fault detecting circuit 40 which monitors the read data 2. Then a microinstruction store control part 50 starts again to invert a reverse signal 3 and reads a microinstruction out of a floppy disk to store it in a memory 20 as the write data 1. At the same time, the data 1 having its plus and minus inverted to each other is written into the memory 20 and the data on '0' is written to the bit where a fault occurs to break the data into '0'. Thus no influence is produced even though the data is broken into '0'. As a result, even a fixed fault can be dealt with.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory circuit in an information processing system,
In particular, the present invention relates to a memory circuit that performs control storage for storing microprograms.

[Conventional technology]

In an information processing device, memory is used in various parts of the device. In particular, in recent years, the number of information processing devices controlled by microprograms has increased, and memories are being used as control storage for storing microinstructions. ROM for control memory
(read-only memory) is sometimes used, but R
Since OM generally has a slow read speed, a device with a fast processing speed often uses a RAM (random access memory) with a fast read speed.

When RAM is used as control memory, a method of storing microinstructions in RAM is to read the microinstructions stored on a floppy disk or ROM when the power is turned off and transfer them to the RAM when the power is turned on. . Furthermore, when a RAM is used as a control memory, a failure may occur that destroys stored data (microinstructions) intermittently or permanently.

Conventionally, countermeasures have been taken against these failures, such as adding an FCC (error check and correction) circuit or rewriting stored data (microinstructions).

Countermeasures against failures that destroy these stored data can be roughly divided into two methods: the first method is to add an FCC circuit and read the read data through the FCC circuit, and the second method is to rewrite the stored data (microinstructions) into the control memory. Two methods are possible.

[Problem to be solved by the invention]

In the conventional memory circuit described above, the first method requires an extra bit for storing the FCC code in the control memory, and the read data is read out after being checked and error corrected through an ECC circuit. The second method has the disadvantage of being slow, but is effective against intermittent failures but is ineffective against fixed failures.

For these reasons, there is a need for a method that does not increase the number of bits in the control memory, does not significantly reduce the read speed, and is effective against not only intermittent failures but also fixed failures.

[Means to solve the problem]

The memory circuit of the present invention is a memory circuit in an information processing system, and includes a rewritable memory, and when an inversion signal from the outside indicates non-inversion, write data from the outside is directly written to the memory. a write data inverting circuit that inverts the sign of the write data from the outside and sends it as write data to the memory when the inverted signal indicates inversion; If the read data from the memory is inverted, the read data from the memory is sent as read data to the outside, and if the read data indicates inversion, the read data from the memory is inverted and sent as read data to the outside. and an inverting circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the structure of an embodiment of the present invention.

The microinstruction storage control unit 50 reads out microinstructions stored in the floppy disk and stores them in the memory 20 when the power is turned on and when a failure occurs. The write data inversion circuit 10 receives an inversion signal 3 from the microinstruction storage control section 50.
If the inversion signal 3 indicates non-inversion, the write data 1 is sent to the memory 20 as is, and if the inversion signal 3 indicates inversion, the write data 1 is sent to the memory 20 with the sign reversed. The memory 20 is a control memory that stores microinstructions, and the write data inversion circuit 10
Write the output of . The read data inversion circuit 30 sends the data from the memory 20 as read data 2 if the inversion signal 3 from the microinstruction storage control unit 50 indicates non-inversion, and sends the data from the memory 20 as read data 2 if the inversion signal 3 indicates inversion. The data is switched between positive and negative and sent as read data to perform various controls inside the device. The fault detection circuit 40 is
A parity check (odd parity check) is performed on the read data 2, and the occurrence of a failure in the read data 2 is monitored.

FIG. 2 is an explanatory diagram illustrating the relationship between the inverted signal 3 and data types (write data 1, data in the memory 20, and read data 2). Here, the least significant bits of the data are parity (odd parity) bits. If "1011" is sent as write data 1 to a certain address in the memory 20 when the inversion signal 3 indicates non-inversion, the memory 2
“1011” is written to this address within 0.

When this address in the memory 20 is then read, "10l1" is output as read data 2. If "1011" is sent as write data 1 to a certain address in the memory 20 when the inversion signal 3 indicates inversion, "0100" is written to this address in the memory 20.

When this address in the memory 20 is then read, "1011" is output as read data 2.

FIG. 3 is a flowchart showing the operation of the microinstruction storage control unit 50 when the power is turned on and when a failure occurs.

First, a description will be given of the process from when the power of the device is turned on until the device enters the normal operating state.

When the device is powered on, the microinstruction storage control unit 50
starts to move and makes the inverted signal 3 non-inverted (step 51
). Then, the microinstruction is read from the floppy disk (step 52) and stored in the sending memory 20 as write data 1 (step 53). The operation from reading the microinstruction to storing it in the memory 20 is as follows:
The process is executed until all microinstructions have been stored (steps 52 to 54). Then, when the storage is completed, the microinstruction storage control section stops operating, and the device enters the normal operating state. When the device enters a normal operating state, microphone commands are sequentially read out from the memory 20 as read data 2, and various parts inside the device are controlled thereby. At this time, the contents of the memory 20 remain as read data 2.
used as.

Next, a description will be given of the process from when a failure occurs in the memory 20 to when the memory 20 returns to its normal operating state.

At a certain address inside the memory 20, the second bit from the bottom of the data “1011” is permanently destroyed to “0” and “1”
001", the failure detection circuit 40 monitoring the read data 2 detects the failure. When the failure is detected, the microinstruction storage control unit 50 starts operating again and outputs an inverted signal. 3 is inverted (step 55). Then, the microinstruction is read from the floppy disk (step 52) and stored in the memory 20 as write data 1 (step 53). This operation is executed until all microinstructions are stored (steps 52 to 54). At this time, data with the sign of write data 1 inverted is written to the memory 20, and the data is destroyed to "0". “
Since data of "0" is written, there is no effect even if the data is destroyed to "0". When the storage is completed, the microinstruction storage control section stops operating and the device returns to the normal operating state. When the device enters the normal operating state, memory 2
Microinstructions are read out sequentially from 0 as read data 2, and each part inside the device is controlled by these microinstructions. At this time, data with the positive and negative contents of the memory 20 swapped is used as read data 2 (microinstruction).

Although the embodiment has been described above in which all write data and all read data are inverted, it is also possible to invert only the write data and read data of only the bit in which a failure has occurred.

〔Effect of the invention〕

As explained above, the present invention is capable of rewriting the microprogram by inverting the sign of write data when a failure occurs in control writing using RAM, and rewriting the microprogram by inverting the sign of read data when reading. This has the effect of being able to deal with not only intermittent failures in the control memory, but also fixed failures, without increasing the number of bits in the control memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram illustrating the relationship between inverted signals and data types (write data, data in memory, and read data), and FIG. 5 is a flowchart showing the operation of the microinstruction storage control unit 50 when the power is turned on and when a failure occurs. 10...Write data inversion circuit, 20...
...Memory, 30... Read data inversion circuit,
40...fault detection circuit, 50...microinstruction storage control unit.

Claims (1)

[Claims] In a memory circuit in an information processing system, there is provided a rewritable memory, and when an inversion signal from the outside indicates non-inversion, write data from the outside is directly used as write data to the memory. a write data inversion circuit that inverts the sign of the write data from the outside and sends it as write data to the memory when the inversion signal is inverted; a read data inversion circuit that sends out the read data from the memory as read data to the outside, and inverts the sign of the read data from the memory and sends it out as read data to the outside if an inversion is indicated; A memory circuit comprising: