JPH0428149B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improved field effect semiconductor device, and particularly to a highly integrated field effect semiconductor device.

[Conventional technology]

Field-effect semiconductor device (hereinafter abbreviated as FET)
In order to improve performance, it is effective to shorten the channel length. However, as the channels become shorter, an undesirable phenomenon called punch-through phenomenon occurs. This will be explained below using a MOS type semiconductor device.

As shown in FIG. 1, a conventional MOS type semiconductor device includes a semiconductor substrate 1, source/drain diffusion regions 2 and 2' formed on this substrate 1, and a gate insulating film 3 formed on the substrate 1. , and a gate electrode 4 provided on this gate insulating film 3. Such a structure is disclosed, for example, in Japanese Patent Publication No. 45-12097.

[Problem that the invention seeks to solve]

In this MOS type semiconductor device, especially in a short channel _MOSFET aimed at high integration, the drain current in the subthreshold region - Gate voltage characteristics deteriorate. That is, a short channel MOS type semiconductor device has an unfavorable characteristic that a punch-through current flows between the source and the drain and the drain current is not completely pinched off compared to a long channel MOS type semiconductor device. For example, in integrated circuits such as dynamic RAM, charge stored as information leaks out due to punch-through current.

This phenomenon is widely seen in junction gate type semiconductor devices, metal-semiconductor contact gate type semiconductor devices, etc., regardless of the MOS type semiconductor device (MOSFET).

The present invention proposes an improved structure that suppresses such punch-through current and allows a short channel field effect semiconductor device to operate favorably.

A conventional MOS type semiconductor device is known to have a structure in which a highly concentrated layer containing impurities of the same type as the substrate is formed at the interface between a gate insulating film and a substrate. However, in such a structure, since punch-through current flows deeper than the high concentration layer, the subthreshold region characteristics are not improved at all and there is no effect. Furthermore, this structure has the disadvantage that the threshold voltage (V _T ) becomes too high due to the highly doped layer, and that V _T fluctuates significantly due to fluctuations in the highly doped layer.

[Means for solving problems]

The semiconductor device of the present invention is a semiconductor device having two or more ohmic electrodes and a controllable electrode, wherein the impurity concentration is higher than the impurity concentration of the base body inside the base body of the semiconductor device, and the conductivity type of each other is higher than the impurity concentration of the base body. It is characterized by comprising first and second impurity thin layers having different impurity layers. More specifically, in order to significantly lower the impurity concentration of the semiconductor substrate, eliminate fluctuations due to the impurity concentration distribution, and suppress the spatial spread of the carrier distribution that causes punch-through current to flow, the interface between the substrate and the insulating film is A thin layer (hereinafter referred to as the first layer) containing a high concentration of impurities of the same conductivity type as the source (or drain) impurities is formed very close to the source (or drain) impurity, and further suppresses the spatial spread of the so-called drain depletion layer. Therefore, by providing one or more thin impurity layers (hereinafter referred to as the second layer) of the opposite conductivity type to the source (or drain) impurities at positions where the potential line tends to spread, punch-through can be suppressed and good characteristics can be exhibited. A short channel field effect semiconductor device is provided.

[Effect]

In a short channel MOS type semiconductor device, a punch-through current flows because the drain depletion layer extends toward the source side and the drain depletion layer and the source depletion layer directly influence each other. Figure 2 shows this situation using computer simulation. In the figure, the equipotential line 5 surrounding the drain 2' bulges toward the source side, and the current 6 flowing near the interface between the substrate and the insulating film without the usual punch-through, It moves away from the interface and spreads in the depth direction of the substrate. The spatial spread of this current distribution becomes more pronounced as the channel length becomes shorter, and therefore a larger punch-through current flows.

In the present invention, two important concepts are clarified in order to suppress punch-through. First, it is important to suppress the spatial spread of the current distribution as shown in Figure 2 and realize a one-dimensional current distribution.

The second is to prevent the bulge of the equipotential lines from extending toward the source side. That is, it is a spatial and electrical shielding effect of the drain electric field.

Regarding a structure that realizes the first concept above,
This is disclosed in a known example (Japanese Unexamined Patent Publication No. 53-95571) etc. by the present inventors. This shows a structure in which a thin layer of impurities of the same conductivity type as the source (or drain) is provided near the surface of the substrate.

In order to simultaneously realize the above two important concepts, at least two special impurity layers are required to be provided on the semiconductor substrate. That is, the first layer is located very close to the interface, and the second layer is located at the location where the potential bulge is greatest, and this second layer must be formed with an impurity of conductivity opposite to that of the source (or drain) impurity. Must be. Moreover, in order to effectively realize the above two concepts, it is necessary to form a layer with a high impurity concentration and a dimensionally thin layer.

Note that if two or more thin impurity layers (second layers) of conductivity type opposite to the source (or drain) impurity are provided in this manner, a drawback arises in that the threshold voltage becomes too high. However, this threshold voltage can be increased by adding a thin layer (first layer) of an impurity of the same conductivity type as the source (or drain) impurity.
Easily controllable.

FIG. 3 shows one result of a computer simulation in which the internal operation of a MOS type semiconductor device according to the present invention was analyzed. As is clear from the figure, the current distribution is limited to the vicinity of the interface, that is, it becomes a one-dimensional distribution (the effect of the first layer), and the potential distribution (contour line representation) also shows a pinning effect on the drain side. (effect of the second layer mentioned above).

Further, FIG. 4 shows the results of the channel length dependence of the threshold voltage obtained by computer simulation. Compared to the conventional structure MOS type semiconductor device 42, the improved MOS type semiconductor device 41 according to the present invention
It can be seen that the threshold voltage fluctuation has been suppressed to the submicron range. Also, as a reference material,
Of the two important concepts mentioned in the present invention, for example, if one lacks the ability to suppress the spatial spread of the potential distribution, that is, a structure that has the above first layer but does not have the above second layer. Analysis result 43
are also shown in Figure 4. As seen in the figure, 2
Only by satisfying these two concepts at the same time will it be possible to produce a short channel MOS type semiconductor device even better.

The shielding effect of this special impurity layer is
Needless to say, it can be applied not only to MOS type devices but also to FET devices in general.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

In the semiconductor device shown in Figure 5, the specific resistance
Using the molecular beam epitaxial method, a very thin p + type silicon substrate 11 doped with boron at an areal density of 1×10 ¹² cm ^-2 was formed on a p-type (100) silicon substrate 11 with a low impurity concentration of about 20 Ω ^· cm. forming layer 12, followed by
P ^-type Si 11' is deposited to a thickness of 300 nm. Here, boron is doped with an areal density of 3×10 ¹² cm ^-2 to form a second p ⁺ type Si layer 13, and p ^- type silicon 11'' is deposited again to a thickness of 15 nm, and then arsenic is doped with an areal density of 2 cm -2. ×
10 ¹² cm ⁻² doped n-type Si layer 14 is formed. Furthermore, p ^- type silicon 11 is deposited to a thickness of 15 nm to form a substrate having three thin layers of n ⁺ , p ⁺ , and p ⁺ types from the surface. In addition, 11′, 11″, 11〓
The specific resistance of No. 11 was set to be approximately the same as that of No. 11.

It has been confirmed that with these manufacturing methods, the effect is weakened if each impurity layer is too thick or too thin. The optimal design value is 10 to 200〓 for the thickness,
Impurity concentration (per unit area) is 1×10 ¹² cm ^-2 ~1
It was in the range of ×10 ¹³ cm ^-2 .

Based on the substrate thus produced, a gate oxide film 15 is formed to a thickness of 20 nm, and a gate electrode 16 is formed. Furthermore, using the gate as a mask, the N ⁺ layers of the source 17 and drain 18 are coated to a depth of 0.3 μm.
A MOS type FET was manufactured by forming the MOS type FET.

The current-voltage characteristics of the above semiconductor device are shown in FIG. 6 (computer simulation). drain voltage is
Up to 5V, no increase in leakage current or drain current due to punch-through occurred.
The effective channel length of this semiconductor device was 0.5 μm. In this way, it has become possible to obtain good electrical characteristics in a short channel MOS type semiconductor device even in a region where normal operation could not be obtained due to punch-through in the conventional structure.

Next, the effectiveness of the present invention will also be demonstrated for gallium arsenide semiconductor devices. FIG. 7 shows a structure in which a highly concentrated thin layer 72 proposed in the present invention is interposed between a semi-insulating (GaAs) substrate 71 and an active layer 73.
It shows the structure of MES type FET. If the highly concentrated thin layer 72 were not present, the equipotential line would be drawn from the drain 76 side toward the source 74 side by the line segment 72, as shown in FIG.
In short channel devices, punch-through occurs. However, the highly concentrated thin layer 7
It was confirmed that by providing 2, the expansion of equipotential lines can be suppressed and punch-through can be prevented. 75 is a gate.

Similar effects are shown to be effective even when the substrate of a semiconductor device is not made of only one type of material, for example, when semiconductors with different band gaps are mixed together.

FIG. 8 shows a semiconductor device having a structure in which a high concentration GaAs thin layer 82 and an intrinsic GaAs layer 83 are sequentially formed on a semi-insulating GaAs substrate 81, and then a gallium aluminum arsenide compound semiconductor layer 84 is provided. FIG. 9 shows a structure in which the gallium-aluminum-arsenide compound semiconductor layer 84 of FIG. 8 is formed into a highly concentrated thin layer 94, and an intrinsic semiconductor (GaAs) layer 95 is further formed. It was confirmed that the characteristics of both semiconductor devices were improved by interposing the highly concentrated thin layer.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a semiconductor device that exhibits good electrical characteristics without causing punch-through down to a submicron region with an effective gate length of 1 μm or less. The goal is to improve the performance of semiconductor devices by shortening the channels.

[Brief explanation of drawings]

FIGS. 1 and 2 are diagrams explaining conventional MOSFETs, FIGS. 3 and 4 are diagrams explaining MOSFETs of the present invention, FIGS. 5, 6, 7, 8, FIG. 9 is a diagram showing an embodiment of the present invention. 11...p ^- type silicon substrate, 11', 11'',
11〓...p ^- type silicon layer, 12, 13...p ⁺
Type silicon thin layer, 14...np ⁺ type silicon thin layer.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate having a pair of impurity regions with a higher concentration than the impurity concentration of the substrate, and at least a region sandwiched between the pair of impurity regions, on the substrate, the pair of impurity regions. In a semiconductor device comprising a controllable electrode that controls a current flowing between regions, a dopant of conductivity type that is higher in concentration than the impurity concentration of the base is located below the controllable electrode inside the base. At least one layer each of different first and second impurity thin layers is provided, the first impurity thin layer is formed to have the same conductivity type as the impurity region, and the second impurity thin layer is opposite to the impurity region. conductivity type, the first impurity thin layer is provided closer to the control electrode than the second impurity thin layer, and the thicknesses of the first and second impurity thin layers are A semiconductor device characterized in that each size is formed to be 10〓 or more and 200〓 or less. 2. The semiconductor according to claim 1, wherein the impurity dose of the first and second thin impurity layers is 1×10 ¹² cm ^-2 or more and 1×10 ¹³ cm ^{-2 or} less. Device. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device including a MOS type field effect transistor having the pair of impurity regions as a source and a drain. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device including a junction field effect transistor in which the pair of impurity regions serve as a source and a drain. 5. Claim 1, wherein the semiconductor device is a semiconductor device including a heterojunction field effect transistor in which the pair of impurity regions are used as a source and a drain, and the base body is made of a plurality of types of materials. The semiconductor device described.