JPH04282914A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a crosstalk voltage caused at control signal changeover of a control circuit of a bi-directional switch circuit. CONSTITUTION:In order to reduce the drive capability of a transistor(TR) being a component of a control circuit 36 controlling a bi-directional switch circuit 35, elements 40, 41, 42, 43 with a low capability are in use and capacitors 38, 39 are provided, When elements 4, 5, 7, 8 whose capability is high, resistors 44, 45 and the capacitors 38, 39 are provided to unsharpen an output waveform of the control circuit 36 thereby suppressing a crosstalk voltage of the control circuit 36.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor integrated circuit device equipped with a bidirectional switch circuit and its control circuit, and more particularly to a semiconductor integrated circuit device that is improved so as to slow down changes in the normal and inverted outputs of control signals of the control circuit.

0002

2. Description of the Related Art FIG. 3 shows a circuit configuration of a conventional semiconductor integrated circuit device of this type. In the figure, 35 is a bidirectional switch circuit, 36 is its control circuit, 1 is a power supply terminal,
2 is a GND terminal, 3 is a P-channel MOSFET (P1
), 4 is P-channel MOSFET (P2), 5 is P-channel MOSFET (P3), 6 is N-channel MOS
FET (N1), 7 is an N-channel MOSFET (N2
), 8 is N-channel MOSFET (N3), 9 is P
1 3, N1 6, 10 is the input terminal of the bidirectional switch circuit 35, 11 is the output terminal of the bidirectional switch circuit 35, 12 is the input resistor R1, 13
is the output resistance R3, and 14 is the output load capacitance C1. Further, 15 is a control input terminal of the control circuit 36, and 16 is an inverter composed of P2 4 and N2 7, the input of which is connected to the control input terminal 15. 17 is an inverter composed of P3 5 and N3 8, and inverters 16 and 17 are connected in cascade with each other. 18 is an output terminal of the inverter 16;
Here, it is connected to the gate of N1 6 of the bidirectional switch 9. 19 is an output terminal of the inverter 17, which is connected to the gate of P13 of the bidirectional switch 9 here.

FIG. 4 is an equivalent circuit of FIG. 3, and in the figure, 1, 2, 10 to 14 indicate the same parts as in FIG. 20 is the resistor R2 of the bidirectional switch 9, 21 is the inverter 17
22 is the ON resistance R5 of N3 8 of the inverter 17, 23 is the P of the inverter 16
2 4 ON resistance R6, 24 is N2 of inverter 16
ON resistance R7 of 7, 25 is a switch indicating the operation of the inverter 17, 26, 27 are terminals of the switch 25, 28 is a switch indicating the operation of the inverter 16, 29, 30 are terminals of the switch 28, 31 is a bidirectional switch 9 P1 3
The parasitic capacitance C2 between the gate of and the input terminal 10,
32 is a capacitance C3 parasitic between the gate of P1 3 and the output terminal 11, 33 is a capacitance C4 parasitic between the gate of N1 6 of the bidirectional switch 9 and the input terminal 10, 34
is the parasitic capacitance C5 between the gate of N1 and the output terminal 11.

FIG. 5 is a timing chart showing changes in each terminal voltage with respect to the voltage V1 applied to the control input terminal 15. V2 is the output voltage of the inverter 16, V
3 is the output voltage of the inverter 17, V4 is the output voltage of the output terminal 1 due to only V2, ignoring the influence of V6 due to V3.
The voltage obtained at the output terminal 11, V5, ignores the effect of V2 on V6, and the voltage obtained at the output terminal 11 only by V3, V6, is the superposition of V4 and V5. Further, t1 indicates the time of the peak value of V4 relative to V1, and t2 indicates the time of the peak value of V5 relative to V1.

Next, the operation will be explained. When the power supply potential, that is, "H" is applied to the control input terminal 15, the output terminal 18 of the inverter 16 goes to the GND potential, that is, "L", and the output terminal 19 of the inverter 17 goes to "H".
, the gate potential of P13 is biased to "H", the gate potential of N16 is biased to "L", and P1 3, N1 6
Both are turned off, and the bidirectional switch 9 cuts off the connection between the input terminal 10 and the output terminal 11 (hereinafter referred to as the OFF state).

On the other hand, "L" is applied to the control input terminal 15.
is applied, the output terminal 18 of the inverter 16 becomes “
"H", the output terminal 19 of the inverter 17 becomes "L", the gate voltage of P1 3 is biased "L", the gate voltage of N1 6 is biased "H", and both P1 3 and N1 6 are turned on. The bidirectional switch 9 connects the input terminal 10 and the output terminal 11 through a composite resistor R2 20 (hereinafter referred to as the ON state).

In this way, the bidirectional switch 9 is turned on.
When changing from the OFF state to the ON state, the voltage at the output terminal 11 causes crosstalk. This will be explained with reference to FIGS. 4 and 5.

When the gate voltage V2 of N16 constituting the bidirectional switch 9 is "H", the capacitance C534 between the gate of N16 and the output terminal 11 has a charge q5 = C5.
×Vcc (power supply voltage) is being charged. Further, since the output load capacitor C1 14 has a charge q1 = 0 and is not charged, V4 is at the GND potential.

When V2 changes from "H" to "L", the charge in the capacitance C5 34 between the output terminals 11 of N1 6 is discharged through the ON resistance R7 24 of N2 7 of the inverter 16, so the output load capacitance C1 14 has a time constant τ1
= C5 × R7, a charge of q1 (MAX) = -q5 appears, V4 is the peak value, -(C5 /C1
)・Vcc. At the same time, the above charge q1 is τ2 =
C1×R3 is discharged to the GND terminal 2 via the output resistor R3 13, and V4 approaches the GND potential. and,
When V2 is "L" and the discharge of the charge q1 = -q5 through the discharge path to the output resistor R3 13 is completed, the capacitance C5 34 between the output terminals 11 and the output load capacitance C1 14 are not charged. V4 becomes the GND potential.

When V2 changes from “L” to “H”, the capacitance C5 34 between the output terminals 11 and P of the inverter 16
Since it is charged by the ON resistance R6 23 of 2 4, the output load capacitance C1 14 has a time constant.

[0011]

[Math 1] charge at

0012

[Math 2] A charge appears, and V4 is the peak value,

[0013]

[Math 3] become. At the same time, the above charge is

[0014]

[Equation 4] Then, it is discharged to the GND terminal 2 via R3 13, and V4 approaches the GND potential. Then, when V2 is “H”, the above charge

[0015]

When the discharge of [Equation 5] is completed, the charge q5 of the capacitance C5 34 between the output terminals 11 = C5 × Vcc, the charge q1 of C1 14
=0, and V4 =0.

Similar to the change in V4 due to the change in V2 described above, the change in V5 with respect to the change in V3 also takes the waveform shown in FIG. . Therefore V4
, V5, which is a superposition of V6, generates a crosstalk voltage by switching the control input signal, as shown in FIG.

[0017]

[Problems to be Solved by the Invention] Since the conventional semiconductor integrated circuit device is constructed as described above, it is necessary to reduce the parasitic capacitance C3 32 between the gate of P1 3 constituting the bidirectional switch 9 and the output terminal 11. N1 6 gate/output terminal 1
There is a problem in that the crosstalk voltage of the output voltage V6 appearing at the output terminal 11 is extremely high due to the charging/discharging current of the parasitic capacitance C5 34 between the terminals 1 and 1.

The present invention has been made to solve the above-mentioned problems, and its object is to obtain a semiconductor integrated circuit device having a bidirectional switch that can obtain an output voltage with low crosstalk voltage. .

[0019]

SUMMARY OF THE INVENTION In a semiconductor integrated circuit device according to the present invention, the drive ability of a transistor forming a control circuit for controlling a bidirectional switch circuit is reduced and its load is increased.

[0020]

[Operation] In this invention, the drive ability of the transistor forming the control circuit that controls the bidirectional switch circuit is reduced and its load is increased, so that the signal that controls the bidirectional switch circuit can be changed gradually. , it is possible to suppress the peak value of crosstalk caused by parasitic capacitance between the gate electrode and the output of the bidirectional switch.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. FIG. 1(a) shows the circuit configuration of a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 1 to 17 indicate the same parts as in FIG. 3. 35 is a bidirectional switch circuit, 36
is a control circuit, 40 and 41 are P-channel MOSFETs with low drive ability, 42 and 43 are N-channel MOSFETs with low drive ability, 38 and 39 are capacitors, and 37
is one electrode of the capacitors 38 and 39.

FIG. 2 is a timing diagram showing changes in each terminal voltage with respect to the input voltage V1 of the control circuit in the circuit of this embodiment. In the figure, the same reference numerals as in FIG. The voltage obtained at the output terminal 18a, V3, is the voltage obtained at the output terminal 19a.

In this embodiment, the bidirectional switch 9 is turned on and off by the outputs of the inverters 16 and 17, as in the conventional example, but the output terminals 18a and 19a of the control circuit 36 have large load capacitances. 38 and 39 are provided, and a P-channel transistor 40 with low drive ability is provided.
, 41 and N-channel transistors 42, 43, the changes in the input voltages V1, V2 are slowed down,
As shown in V4 and V5 in FIG. 5, the peak value of the differential waveform can be suppressed low, and the crosstalk voltage of V6 becomes small.

In the above embodiment, the P channel transistor 40 in the control circuit 36 is used to slow down the changes in the waveforms V2 and V3 of the control circuit 36.
, 41 and N-channel transistors 42, 43 with low drive ability, but as shown in FIG. The drive capability may be lowered by connecting the two, and the same effect as in the above embodiment can be obtained.

[0025]

As described above, according to the semiconductor integrated circuit device of the present invention, the drive ability of the transistor forming the control circuit that controls the bidirectional switch circuit is lowered and its load is increased, so that This has the effect of providing a low talk voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing the circuit configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing changes in voltage at each terminal with respect to input voltage of a control circuit of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a circuit configuration diagram showing the circuit configuration of a conventional semiconductor integrated circuit device.

FIG. 4 is an equivalent circuit diagram showing an equivalent circuit of a conventional semiconductor integrated circuit device.

FIG. 5 is a timing diagram showing changes in each terminal voltage with respect to input voltage of a control circuit of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

Claims (1)

[Claims] [Claim 1] Consisting of a P-channel MOSFET and an N-channel MOSFET, the input and output terminals are cut off,
In a semiconductor integrated circuit device comprising a bidirectional switch circuit for conducting, and a control circuit for controlling the bidirectional switch circuit and outputting a control signal for normal rotation and inversion, the control circuit outputs normal rotation and inversion for the control signal. A semiconductor integrated circuit device characterized in that an inverted output changes slowly.