JPH04286012A - Power-on reset device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset device that corrects manufacturing process variations and generates stable pulses when power is turned on.

0002

2. Description of the Related Art Conventionally, power-on reset circuits have been used in semiconductors to generate pulses for resetting internal devices when power is turned on.

FIG. 3 is a circuit diagram of a conventional power-on reset device, in which the source of a P-channel transistor P5 is connected to a power supply, its gate is connected to its drain, and a capacitor C
2 to ground. The source of N-channel transistor N3 is connected to ground, and its gate is connected to P
The gate and drain of channel transistor P5 are connected to node 3, and N-channel transistor N
The drain of N-channel transistor N3 is connected to the power supply via a capacitor, and the drain of N-channel transistor N3 is used as an output.

The operation of the conventional power-on reset device configured as described above will be explained below.

[0005] Since the P-channel transistor P5 has its gate and drain connected, it can be regarded as a resistor. Then, when the power is turned on, current flows into the capacitor C2 through the P-channel transistor P5. However,
While the charge is stored in the capacitor C2, the potential of the node 3 is lower than the potential of the power supply and becomes L level. Here, node 3 is closer to the ground than the power supply VDD, and although the N-channel transistor N3 whose gate is connected to node 3 is in a cut state, it is not completely cut, and is equivalent to a high resistance. Since a small current is flowing, an H level is output to the node OUT due to the charging current to the capacitor C3.

However, when sufficient charge is stored in the capacitor C2, the node 3 becomes H level, and the N-channel transistor N3 is turned on, so that an L level is output. By the above operation, an H level pulse is generated at the node OUT when the power is turned on.

[0007]

However, the conventional device described above cannot cope with variations in the threshold voltage of transistors caused by the manufacturing process, and the power supply level at which pulses are generated continues to fluctuate. However, as semiconductor voltages have become lower, fluctuations in the power supply level for pulse generation have become a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a power-on reset device that corrects variations in the power supply level at which pulses are generated due to variations in threshold values caused by processes. shall be.

[0009]

[Means for Solving the Problem] In order to achieve this object, the power-on reset device of the present invention uses two P-channel transistors and has a configuration in which the output change of the first stage is canceled out by the second stage. are doing.

0010

According to the present invention, with the above-described structure, the power supply level at which pulses are generated is kept constant against fluctuations in the threshold value due to processes, so that operation at a low voltage is guaranteed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A power-on reset device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a circuit diagram of a power-on reset device according to an embodiment of the present invention. In this embodiment, the gate of N-channel transistor N1 is connected to node 2 as a capacitor, and its source and drain are connected to ground, and the source of N-channel transistor N2 is connected to ground as a resistor, and its gate and drain are connected to node 2. is connected to node OUT.

The operation of this embodiment, which is constructed as described above, will now be explained. In the P-channel transistor P3, the relational expression between voltage and current is as shown in equation (1).

[0014]

[Math 1]

Here, ID indicates the current flowing through P3 of the P-channel transistor, βP indicates the gain coefficient of the P-channel transistor, VIN indicates the gate voltage, and VD
D indicates the power supply voltage, and VTP indicates the threshold voltage of the P-channel transistor. Then, the power supply voltage VDD is P
If it is not above the threshold of channel transistor P3,
Since no current flows through the P-channel transistor P3 in the off state, equation (1) holds true under the condition of VDD>VTP. Furthermore, the gate of P-channel transistor P3 is
Since it is connected to the ground, equation (1) becomes equation (2).

[0016]

[Math 2]

Next, the switching voltage VIN of the P-channel transistor P4 can be expressed as shown in equation (3).

VIN=VDD+VTP...(3) When the power is turned on, a current I flows through the P-channel transistor P3.
D flows, and charge begins to be stored in the capacitor N1. and,
Until the amount of charge is saturated, node 2 is at L level, P-channel transistor P4 whose gate is connected to node 2 is turned on, and an H pulse is applied to both ends of N-channel transistor N2, which acts as a resistor, that is, to the OUT node. Output. When the amount of charge in the capacitor is saturated, node 2
becomes H level, P channel transistor P4 is turned off, and the OUT node becomes L level.

Assume now that the threshold value of the P-channel transistor changes by ΔVTP. At this time, equation (2) becomes equation (4).

[0020]

[Math 3]

The voltage V2 at the node 2 is expressed by equation (5).

[0022]

[Math 4]

Here, CO is an N-channel transistor N
This is the capacity of 1. Furthermore, equation (3) becomes equation (6).

[0024]VIN=VDD+VTP+ΔVTP...(
6) From equations (5) and (6), P channel transistor P
When the threshold value of 3 increases by ΔVTP, the voltage at node 2 changes to a higher direction, but the switching voltage of the P-channel transistor P4, which uses node 2 as its gate, also changes to a higher direction to cancel the increase. Become. vice versa,
When the threshold value decreases by ΔVTP, the voltage at node 2 also changes in a lower direction, but the switching voltage also changes in a lower direction to cancel it out.

In the above embodiment, N-channel transistors are used for the capacitance and resistance, but P-channel transistors may be used instead of the N-channel transistors. In this case, the connection may be the same as that when used as a capacitor, and when used as a resistor, the gate may be connected to ground.

Although the above-mentioned practical circuit is constructed entirely of transistors, it is obvious that it can be equivalently replaced with the circuit shown in FIG.

[0027]

[Effects of the Invention] The present invention realizes a power-on reset device that corrects variations in threshold values and generates pulses stably even at low voltages by configuring a circuit using P-channel transistors, capacitors, and resistors. It is possible.

[Brief explanation of the drawing]

[Fig. 1] Equivalent circuit diagram of a power-on reset device according to the present invention

[Fig. 2] Circuit diagram of a power-on reset device according to another embodiment

[Figure 3] Circuit diagram of a conventional power-on reset circuit

[Explanation of symbols] P1 to P4 P channel transistors N1, N2
N-channel transistor C1 Capacitor (capacitance) R1 Resistor VDD Power supply OUT Output

Claims (2)

[Claims] Claim 1: The source of a first P-channel transistor is connected to a power source, its gate is connected to ground, its drain is connected to ground via a capacitor, the source of a second P-channel transistor is connected to a power source, and its gate is connected to ground. The gate is connected to the drain of the first P-channel transistor, and the drain is connected to ground through a resistor, and the drain of the second P-channel transistor is used as an output, and a pulse is generated at this output when the power is turned on. A power-on reset device configured as follows. 2. The power-on reset device according to claim 1, wherein the capacitance and resistance are obtained by transistors.