JPH04287331A - Manufacture of heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE:To obtain a manufacturing method of a flattened heterojunction bipolar transistor excellent in characteristics. CONSTITUTION:A subcollector layer 2, a collector layer 3, a base layer 4 and emitter layers 5, 6 are grown in order on a sustrate 1, in the manner in which at least one out of a collector junction and an emitter junction becomes a heterojunction. An insulated region 8 having a depth reaching the collector layer 3 is formed in a collector leading-out region by ion implantation. A tapered aperture 13 having a depth reaching the subcollector layer 2 is formed by selectively etching the insulated region 8. Electrode metal 14, 15 is formed by physical deposition method. A collector electrode higher than the depth of the aperture 13 is so formed by lift-off working that a gap is left around said electrode. Then an insulating film 16 is so deposited that the surface is flattened. Said film is buried and formed in the gap around the collector electrode by etching.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a planar structure heterojunction bipolar transistor suitable for miniaturization and high integration.

0002

2. Description of the Related Art Conventionally, a heterojunction bipolar transistor using a GaAs-based compound semiconductor is constructed as shown in FIG. 4, for example. This is created as follows. n+ type GaAs is placed on the semi-insulating GaAs substrate 21.
Sub-collector layer 22, n-type GaAs collector layer 23, p
+ type GaAs base layer 24, n type AlGaAs emitter layer 25, and n + type cap layer 26 are formed by MBE method or MOC.
The layers are sequentially deposited using the VD method. Next, base layer 2
4 and the sub-collector layer 22, and the emitter cap layer 26, base layer 24, sub-collector layer 22
An emitter electrode 27, a base electrode 28, and a collector electrode 29 are formed on each of the substrates.

[0003] As described above, in a heterojunction bipolar transistor manufactured by the conventional method, unevenness is formed on the surface because mesa etching is performed to expose the surface for forming electrodes. When integrating fine heterojunction bipolar transistors, these irregularities cause disconnections in the wiring, which is a problem in integration.

[0004] Therefore, in order to advance the integration of heterojunction bipolar transistors, a planar structure is also being considered. For example, after each semiconductor layer is grown, insulating regions are formed in the base-collector isolation region (collector extraction region) and the element isolation region by ion implantation. Then, an opening is opened in the insulated region of the collector extraction region to expose the sub-collector layer, and a collector electrode is formed there.

[0005] Even with this method, a step of about 1 to 1.3 μm is formed in the portion where the collector electrode is formed. Therefore, if left as is, disconnection will still be a problem when connecting the collector electrode to the wiring. To solve this problem, the collector electrode metal is grown by selective chemical vapor deposition.
It has been proposed to embed it in an opening made in an insulated region (for example, Japanese Patent Laid-Open No. 1-166558).

However, when using chemical vapor deposition, it is necessary to maintain the substrate at a high temperature of about 500°C.
There was a problem that a good collector electrode with sufficiently low contact resistance could not be obtained.

[0007]

[Problems to be Solved by the Invention] As described above, when chemical vapor deposition is used to bury the collector electrode in order to planarize a heterojunction bipolar transistor, the collector contact resistance becomes large and an excellent There was a problem that the characteristics could not be obtained. In view of the above points, it is an object of the present invention to provide a method for manufacturing a flattened heterojunction bipolar transistor having excellent characteristics.

[0008]

[Means for Solving the Problems] A method for manufacturing a heterojunction bipolar transistor according to the present invention includes first applying a high concentration of a first conductivity type on a semiconductor substrate so that at least one of the collector junction and the emitter junction becomes a heterojunction. A sub-collector layer, a first conductivity type collector layer, a second conductivity type base layer and a first conductivity type emitter layer are epitaxially grown in sequence. Ion implantation is performed in the collector extraction region to form an insulating region deep enough to reach the collector layer. This insulated region is then selectively etched to open a tapered opening deep enough to reach the sub-collector layer. Next, by forming electrode metal by physical deposition and lift-off processing, a collector electrode higher than the depth of the opening is formed with a gap left around it, and then an insulating film is deposited so that the surface is flat. By etching this, an insulating film is buried in the gap around the collector electrode.

The step of forming the collector electrode is preferably performed as follows. After forming a first electrode metal film for ohmic contact with the mask remaining and forming a thick second electrode metal film for interconnection via a barrier metal film thereon, the mask is removed. Perform lift-off processing.

0010

According to the present invention, since the collector electrode metal is formed by a physical deposition method, it is not necessary to heat the substrate to a high temperature, and a collector electrode with good ohmic characteristics can be obtained. Further, the collector electrode metal is formed in the tapered opening to have a thickness equal to or greater than the depth of the tapered opening by lift-off processing, and then the gap around the collector electrode is filled with an insulating film. Therefore, a heterojunction bipolar transistor with a completely planarized structure is obtained.

[0011]

Embodiments Hereinafter, embodiments will be described with reference to the drawings.

FIGS. 1 to 3 show Ga according to an embodiment of the present invention.
This is a manufacturing process of an As-based heterojunction bipolar transistor. In this embodiment, both the emitter junction and the collector junction are heterojunctions.

As shown in FIG. 1(a), semi-insulating Ga
On the As substrate 1, by MBE method or MOCVD method,
500nm n+ type GaAs subcollector layer 2,60
0 nm n-type AlGaAs collector layer 3, 100 nm p+ type GaAs base layer 4, 150 nm n-type AlG
An aAs emitter layer 5 and a 100 nm thick n+ type GaAs emitter/cap layer 6 are sequentially deposited.

Next, by selectively implanting B+ ions, an insulating region 7 with a depth reaching the substrate 1 is formed in the element isolation region.
The base is formed by selective ion implantation of H+.
An insulating region 8 having a depth reaching the collector layer 3 is formed in the inter-collector isolation region.

Thereafter, as shown in FIG. 1(b), a silicon oxide film mask corresponding to the emitter pattern is formed using ordinary lithography technology, and unnecessary portions of the emitter/cap layer 6 and the emitter layer 5 are etched. Then, the base layer 4 is exposed. and the exposed base layer 4
An AuZn base electrode 9 is formed on the emitter cap layer 6, and an AuGe emitter electrode 10 is formed on the emitter/cap layer 6 using lithography technology and a spacer lift-off method. Note that the etching process for patterning the emitter and exposing the base layer may be performed before the process for forming the insulating regions 7 and 8.

Next, as shown in FIG. 2(a), a silicon oxide film 11 with a thickness of 500 to 600 nm is formed on the surface of the substrate by CVD.
A photoresist pattern 12 having a window in the collector extraction region is formed thereon. Then, the oxide film 11 is etched by a reactive ion etching method using a gas such as CF4, and then side etched by about 200 nm by chemical etching.

Next, as shown in FIG. 2(b), using the photoresist pattern 12 and the oxide film 11 as a mask, the insulating region 8 is exposed to the subcollector layer 2 by chemical etching using tartaric acid or the like. A deep opening 13 is formed. The opening 13 is tapered as shown.

Next, a physical deposition method such as a vacuum evaporation method or a sputtering method is used to form an ohmic electrode of the collector.
After forming the first collector electrode metal film 14 such as uGe and forming a thin barrier metal such as Mo on it, Ti/P
A second collector metal film 15 for wiring connection such as t/Au is formed to be thick. first and second collector electrode metal films 14,
The total thickness of the holes 15 is equal to or greater than the depth of the opening 13, and is, for example, 100 to 200 nm higher than the substrate surface. Then, a lift-off process is performed by removing the photoresist pattern 12, leaving the collector electrode metal films 14 and 15 in the opening 13. Next, as shown in FIG. 3(a), an insulating film 16 made of polyimide or the like is formed so as to have a flat surface.

Then, the entire surface of the insulating film 16 is etched by a reactive ion etching method using O2 gas.
The surface of collector electrode metal film 15 is exposed. Figure 3(b)
), the polyimide insulating film 16 is left to fill the gap around the collector electrode metal films 14 and 15. Thereafter, after removing the silicon oxide film 11 by etching, the polyimide insulating film 16 is hardened by heat treatment at 320° C. for 20 minutes, and then the collector electrode portion is alloyed by heat treatment at 350° C. for 30 seconds.

Thus, according to this embodiment, a heterojunction bipolar transistor is obtained in which the collector contact opening having a large step is completely buried and planarized. Therefore, it is possible to obtain an integrated circuit having highly reliable wiring with no wiring breaks or the like. Furthermore, since the collector electrode metal film is formed by a physical deposition method, there is no need to keep the substrate at a high temperature during film deposition, and good ohmic contact characteristics can be obtained. The present invention is not limited to the above embodiments.

For example, in the embodiment, the emitter and base electrodes are formed before forming the collector electrode, but the emitter and base electrodes may be formed after forming the collector electrode and filling the periphery with an insulating film. Also in the base electrode part,
Since there is a level difference, although not as large as the collector electrode part, it can be buried flat using the same process as the collector electrode part forming process of the embodiment, thereby achieving further planarization. In the embodiment, both the emitter junction and the collector junction are heterojunctions, but the present invention is also effective even if either one of them is a heterojunction. In the embodiment, a polyimide insulating film was used to fill the collector opening, but other organic or inorganic insulating films may also be used. The collector electrode metal film may also have only one layer instead of the multilayer structure as in the embodiment. In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

[0022]

As described above, according to the present invention, it is possible to obtain a heterojunction bipolar transistor having a flattened structure suitable for high integration and having excellent ohmic contact characteristics of the collector electrode.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a manufacturing process of a heterojunction bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a heterojunction bipolar transistor according to an embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of a heterojunction bipolar transistor according to an embodiment of the present invention.

FIG. 4 is a diagram showing a conventional mesa-type heterojunction bipolar transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1...Semi-insulating GaAs substrate, 2...n+ type GaAs sub-collector layer, 3...n type AlGaAs collector layer, 4...p+ type GaAs base layer, 5...n type AlGaAs emitter layer, 6...n+ type GaAs emitter/cap layer, 7... Insulating region (element isolation region), , 8... Insulating region (collector extraction region), 9... Base electrode, 10... Emitter electrode, 11... Silicon oxide film, 12... Photoresist pattern, 13... Opening, 14...First collector electrode metal film, 15...Second collector electrode metal film, 16...Polyimide insulating film.

Claims (1)

[Claims] Claim 1: A semiconductor substrate having at least one of a collector junction and an emitter junction as a heterojunction;
A step of sequentially epitaxially growing a highly doped sub-collector layer of a first conductivity type, a collector layer of a first conductivity type, a base layer of a second conductivity type, and an emitter layer of a first conductivity type, and performing ion implantation into a collector extraction region to form the collector layer. forming an insulating region with a depth of 100 nm, selectively etching the insulating region using a mask to open a tapered opening with a depth reaching the sub-collector layer, and forming an electrode metal by a physical deposition method. A process of forming a collector electrode metal higher than the depth of the opening in the opening with a gap left around it by formation and lift-off processing, and depositing an insulating film so that the surface is flat. A method for manufacturing a heterojunction bipolar transistor, comprising the step of embedding an insulating film in a gap around the collector electrode metal by etching.