JPH04287973A - Manufacture of compound semiconductor device - Google Patents

Manufacture of compound semiconductor device

Info

Publication number
JPH04287973A
JPH04287973A JP3578091A JP3578091A JPH04287973A JP H04287973 A JPH04287973 A JP H04287973A JP 3578091 A JP3578091 A JP 3578091A JP 3578091 A JP3578091 A JP 3578091A JP H04287973 A JPH04287973 A JP H04287973A
Authority
JP
Japan
Prior art keywords
layer
compound semiconductor
semiconductor device
ohmic electrode
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3578091A
Other languages
Japanese (ja)
Inventor
Takayuki Fujii
隆行 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3578091A priority Critical patent/JPH04287973A/en
Publication of JPH04287973A publication Critical patent/JPH04287973A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To stably form a heat resistant ohmic electrode having a low resistance thereof itself. CONSTITUTION:After an insulating film 2 opened at a desired ohmic electrode part is formed, an Ni4/Ge5 layer is deposited on the electrode part by a lifting- off method. Then, a high melting point metal layer of W6 or the like is selectively formed on the Ge5 by a CVD method, and annealed at about 600 deg.C to form an ohmic electrode. Extraction of As at the time of heat treating can be prevented.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は、化合物半導体装置の
製造方法に関し、特にAuを使用しない耐熱性オーミッ
ク電極形成法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a compound semiconductor device, and more particularly to a method of forming a heat-resistant ohmic electrode without using Au.

【0002】0002

【従来の技術】図4〜6は従来の化合物半導体装置の製
造方法を工程順に示す第4〜6工程断面図であり、図に
おいて、1はGaAs基板、2は絶縁膜、3はホトレジ
スト、7はAuGe共晶、8はNi層、9はAu層であ
る。
2. Description of the Related Art FIGS. 4 to 6 are cross-sectional views showing steps 4 to 6 of a conventional method for manufacturing a compound semiconductor device in the order of steps. In the figures, 1 is a GaAs substrate, 2 is an insulating film, 3 is a photoresist, and 7 is an AuGe eutectic, 8 is a Ni layer, and 9 is an Au layer.

【0003】まず、図4に示すように能動層を形成した
GaAs基板1上にプラズマCVD(Chemical
 Vapor deposition)法などにより全
面に絶縁膜2を形成し、転写技術により所望のドレイン
電極・ソース電極部分が開口するようにホトレジスト3
を形成する。
First, as shown in FIG. 4, plasma CVD (Chemical
An insulating film 2 is formed on the entire surface using a vapor deposition method, etc., and a photoresist 3 is formed using a transfer technique so that the desired drain electrode/source electrode portions are opened.
form.

【0004】次に図5に示すようにホトレジスト3をマ
スクにRIE(reactive−ion  etch
ing )法などにより絶縁膜2のエッチングを行ない
、AuGe共晶7Ni層8Au層9を順次蒸着した後、
図6に示すようにホトレジスト3をアセトンなどで除去
することにより、ソース電極とドレイン電極部分にのみ
金層層を残し400 ℃程度の熱処理(以下、シンタと
称す)を行なうことによりオーミック電極を形成する。
Next, as shown in FIG. 5, RIE (reactive-ion etch) is performed using the photoresist 3 as a mask.
After etching the insulating film 2 by a method such as ing) and sequentially depositing AuGe eutectic 7 Ni layer 8 Au layer 9,
As shown in Figure 6, by removing the photoresist 3 with acetone or the like, a gold layer is left only on the source and drain electrodes, and heat treatment at about 400°C (hereinafter referred to as sintering) is performed to form an ohmic electrode. do.

【0005】このような方法ではオーミック電極部分に
Auを使用しているため配線金属にAlを使用した場合
AuとAlが反応してしまうため配線金属にAlを使用
することができない。そのためNi層Ge層だけでオー
ミック電極を形成することは可能であるが、シンタ温度
が600℃程度となるためAs抜けが発生したりオーミ
ック電極自体の抵抗が高くなるため実用化が困難であっ
た。
[0005] In this method, since Au is used for the ohmic electrode portion, if Al is used for the wiring metal, Au and Al will react, so Al cannot be used for the wiring metal. Therefore, it is possible to form an ohmic electrode using only the Ni layer and the Ge layer, but since the sintering temperature is around 600°C, As dropout occurs and the resistance of the ohmic electrode itself becomes high, making it difficult to put it into practical use. .

【0006】この解決策として、Ni層,Ge層,高融
点金属層を順次蒸着し高融点金属をキャップとしシンタ
する方法が考えられるが、高融点金属はストレスが大き
いため1000Å以上蒸着すると蒸着中にホトレジスト
が変形してしまい安定して形成することができない。
One possible solution to this problem is to deposit a Ni layer, a Ge layer, and a high-melting point metal layer in sequence and sinter using the high-melting point metal as a cap.However, since high-melting point metals have a large stress, if they are deposited with a thickness of 1000 Å or more, the deposition process may be interrupted. The photoresist is deformed and cannot be stably formed.

【0007】[0007]

【発明が解決しようとする課題】このように従来のオー
ミック電極では配線金属としてAlを用いることができ
ず、またNi・Geだけで安定して電極自体の抵抗が充
分低いオーミック電極を形成することができないなどの
問題点があった。
[Problems to be Solved by the Invention] As described above, it is not possible to use Al as a wiring metal in conventional ohmic electrodes, and it is difficult to form ohmic electrodes that are stable and have sufficiently low resistance using only Ni/Ge. There were problems such as not being able to.

【0008】この発明は上記のような問題点を解決する
ためになされたもので、Auを使用せずに電極自体の抵
抗が充分低いオーミック電極を形成できる化合物半導体
装置の製造方法を提供することを目的とする。
The present invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a method for manufacturing a compound semiconductor device that can form an ohmic electrode whose resistance is sufficiently low without using Au. With the goal.

【0009】[0009]

【課題を解決するための手段】この発明に係る半導体装
置の製造方法は、化合物半導体基板上に形成された能動
層上に絶縁膜を堆積させた後ソース電極及びドレイン電
極部分を開口する工程、該開口部分にGe/Ni層を形
成する工程、上記Ge/Ni層上にW−CVD法により
W層を形成する工程、熱処理を行なうことによりオーミ
ック特性を得る工程を含むものである。
[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes the steps of: depositing an insulating film on an active layer formed on a compound semiconductor substrate; and then opening source and drain electrode portions; The method includes a step of forming a Ge/Ni layer in the opening, a step of forming a W layer on the Ge/Ni layer by W-CVD, and a step of obtaining ohmic characteristics by performing heat treatment.

【0010】0010

【作用】この発明においては安定して1000Å以上の
高融点金属層を形成することができるため、オーミック
電極自体の抵抗を低くすることができ、シンタ時のAs
抜けも防止することができる。
[Function] In this invention, since a high melting point metal layer of 1000 Å or more can be stably formed, the resistance of the ohmic electrode itself can be lowered, and As
It can also prevent it from coming off.

【0011】[0011]

【実施例】実施例1. 以下、この発明の一実施例を図について説明する。図1
〜3はこの発明の一実施例による半導体装置の製造方法
を工程順に示す第1〜3工程断面図である。図において
、1〜3は図4〜6と同様であり、4はNi層、5はG
e層、6はW層である。
[Example] Example 1. An embodiment of the present invention will be described below with reference to the drawings. Figure 1
3 are sectional views of the first to third steps showing the method of manufacturing a semiconductor device according to an embodiment of the present invention in order of steps. In the figure, 1 to 3 are the same as in Figures 4 to 6, 4 is a Ni layer, and 5 is a G
The e layer and 6 are the W layer.

【0012】図1に示すように能動層が形成されたGa
As基板1上にプラズマCVD法などにより全面に絶縁
膜2を形成し転写技術により所望のドレイン電極ソース
電極部分が開口するようにホトレジスト3を形成する。
[0012] As shown in FIG.
An insulating film 2 is formed on the entire surface of the As substrate 1 by a plasma CVD method or the like, and a photoresist 3 is formed by a transfer technique so that desired drain and source electrode portions are opened.

【0013】次に、図2に示すようにホトレジスト3を
マスクにRIE法などにより絶縁膜2のエッチングを行
ない、Ni層4Ge層5を蒸着する。
Next, as shown in FIG. 2, the insulating film 2 is etched by RIE using the photoresist 3 as a mask, and a Ni layer 4 and a Ge layer 5 are deposited.

【0014】次に、ホトレジスト3をアセトンなどによ
り除去することによりソース電極・ドレイン電極部分に
のみ金属層を残した後、図3に示すようにW−CVD法
により選択的にGe層上にW層を形成し、600 ℃程
度のシンタを行なうことによりオーミック電極を形成す
る。
Next, after removing the photoresist 3 with acetone or the like to leave a metal layer only on the source and drain electrodes, W-CVD is selectively applied to the Ge layer as shown in FIG. An ohmic electrode is formed by forming a layer and sintering at about 600°C.

【0015】なお、上記実施例ではNi・Ge層を用い
た場合について説明したが、Ni・In層を用いる場合
にも適用できる。
[0015] In the above embodiment, the case where a Ni/Ge layer is used has been described, but the present invention can also be applied to a case where a Ni/In layer is used.

【0016】また、W−CVD法によりW層を形成した
場合について説明したがCVD法によりた層など他の高
融点金属層を形成してもよい。
Further, although the case where the W layer is formed by the W-CVD method has been described, other high melting point metal layers such as a layer by the CVD method may be formed.

【0017】[0017]

【発明の効果】以上のようにこの発明によれば安定して
高融点金属層を1000Å以上形成することができるた
め、オーミック電極自体の抵抗が低減でき、また600
 ℃以上のアニールを行なってもAs抜けを防止するこ
とができる。
As described above, according to the present invention, it is possible to stably form a high melting point metal layer with a thickness of 1000 Å or more, so the resistance of the ohmic electrode itself can be reduced.
Even if annealing is performed at a temperature higher than .degree. C., As loss can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】この発明の一実施例による化合物半導体装置の
製造方法を工程順に示す第1工程断面図である。
FIG. 1 is a first step cross-sectional view showing a method for manufacturing a compound semiconductor device according to an embodiment of the present invention in order of steps.

【図2】この発明の一実施例による化合物半導体装置の
製造方法を工程順に示す第2工程断面図である。
FIG. 2 is a second step cross-sectional view showing the method for manufacturing a compound semiconductor device according to an embodiment of the present invention in order of steps;

【図3】この発明の一実施例による化合物半導体装置の
製造方法を工程順に示す第3工程断面図である。
FIG. 3 is a third step cross-sectional view showing the method for manufacturing a compound semiconductor device according to an embodiment of the present invention in order of steps;

【図4】従来の化合物半導体装置の製造方法を工程順に
示す第1工程断面図である。
FIG. 4 is a first step cross-sectional view showing the conventional method for manufacturing a compound semiconductor device in order of steps.

【図5】従来の化合物半導体装置の製造方法を工程順に
示す第2工程断面図である。
FIG. 5 is a second step cross-sectional view showing the conventional method for manufacturing a compound semiconductor device in order of steps.

【図6】従来の化合物半導体装置の製造方法を工程順に
示す第3工程断面図である。
FIG. 6 is a third step cross-sectional view showing the conventional method for manufacturing a compound semiconductor device in order of steps.

【符号の説明】[Explanation of symbols]

1  GaAs基板 2  絶縁膜 3  ホトレジスト 4  Ni層 5  Ge層 6  W層 7  AuGe共晶 8  Ni層 9  Au層 1 GaAs substrate 2 Insulating film 3 Photoresist 4 Ni layer 5 Ge layer 6 W layer 7 AuGe eutectic 8 Ni layer 9 Au layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  化合物半導体基板上に形成された能動
層上に絶縁膜を堆積させた後ソース電極及びドレイン電
極部分を開口する工程、該開口部分にGe/Ni層を形
成する工程、上記Ge/Ni層上にW−CVD法により
W層を形成する工程、熱処理を行なうことによりオーミ
ック特性を得る工程を含むことを特徴とする化合物半導
体装置の製造方法。
1. A step of opening source and drain electrode portions after depositing an insulating film on an active layer formed on a compound semiconductor substrate, a step of forming a Ge/Ni layer in the opening portions, and a step of forming a Ge/Ni layer in the opening portions. 1. A method for manufacturing a compound semiconductor device, comprising the steps of: forming a W layer on the /Ni layer by W-CVD; and obtaining ohmic characteristics by heat treatment.
JP3578091A 1991-03-01 1991-03-01 Manufacture of compound semiconductor device Pending JPH04287973A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3578091A JPH04287973A (en) 1991-03-01 1991-03-01 Manufacture of compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3578091A JPH04287973A (en) 1991-03-01 1991-03-01 Manufacture of compound semiconductor device

Publications (1)

Publication Number Publication Date
JPH04287973A true JPH04287973A (en) 1992-10-13

Family

ID=12451416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3578091A Pending JPH04287973A (en) 1991-03-01 1991-03-01 Manufacture of compound semiconductor device

Country Status (1)

Country Link
JP (1) JPH04287973A (en)

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