JPH0541383A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] [Purpose] Epitaxial base bipolar transistor
For the manufacturing method of the
The purpose is to stably manufacture offspring. [Structure] Si on the epi base layer 2₃N_FourMembrane 3 and SiO₂With membrane 4
Deposit poly-Si film 5 and deposit poly-Si film 5 and SiO₂Intrinsic film on membrane 4
Forming a base window 6 defining a source region 2i,
Poly-Si film 7 is formed only on the side surface, and Si is₃N_FourShape membrane 8
Formed outside the transistor area 9₃N_FourFilm 8 and poly-Si film
5 removed, SiO₂The film 4 is removed and the poly-Si films 5 and 7 are oxidized.
Then SiO₂Without membrane 10, Si₃N_FourMembrane 8 and intrinsic base region 2i
Other than Si ₃N_FourRemove the membrane 3 and expose it on the exposed base layer 2
SiO₂Poly for the base extraction electrode having a thickness reaching the lower surface of the film 10
A Si film 11 is formed and Si is formed on the entire surface.₃N_FourForm membrane 12 and
On the electrode forming area 13₃N_FourMembrane 12 and Si₃N_FourRemove 3
So as to expose the intrinsic base region 2i surface
To configure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, particularly an epitaxial base having a very thin base formed by epitaxial growth (hereinafter referred to as an epi base).
The present invention relates to a method for manufacturing a bipolar transistor.

In order to improve the performance of a semiconductor integrated circuit, it is required to form a semiconductor element having excellent high speed performance. For that purpose, the cutoff frequency is improved by making the base shallow by epitaxial growth, and
It is necessary to reduce parasitics and improve overall device speed by introducing a self-aligned process.

[0003]

2. Description of the Related Art In a conventional method of forming an epi-base bipolar transistor, a self-alignment process called double poly self-alignment has been developed and used in order to reduce the parasitic element portion.

This conventional method, as shown in FIG.
For example, after the p-type epi base layer 52 is formed on the n-type collector layer 51, the p-type epi base layer 52 to be a base electrode is formed on the base layer 52.
^{A +} type polysilicon film is formed, and a first silicon oxide (SiO ₂ ) film 54 is formed on the p ⁺ type polysilicon film 153.
Then, a base window 55 penetrating the first SiO ₂ film 54 and the polysilicon film 153 and defining the intrinsic base region 52i of the base layer 52 is formed by anisotropic etching means. By this patterning, the p ⁺ type polycrystalline silicon film 153 becomes the p ⁺ type polysilicon base electrode 53.

Next, as shown in FIG. 5 (b), the base window is
A SiO ₂ side wall composed of a _second SiO ₂ film on the side surface of 55
Then, an emitter electrode 57 made of n ⁺ type polysilicon is formed on the base window 55, and then heat treatment is performed, and solid phase diffusion of impurities from the emitter electrode 57 is performed as shown in FIG. 5C. This is a method of forming an n ⁺ type emitter region 58 in the p type intrinsic base region 52i and forming ap ^{+ type} external base region 59 in the p type base layer 52 by solid phase diffusion of impurities from the base electrode 53. ..

[0006]

The purpose of the epi-base bipolar transistor is to reduce the base width and increase the speed, and therefore the base layer 52 is formed very thin.

Therefore, according to the above-mentioned conventional method, as shown in FIG.
In the anisotropic etching process for forming the base window 55 in the p ⁺ type polysilicon film 153 described with reference to (a),
Since there is no etching selectivity between the p ⁺ -type polysilicon film 153 and the p-type base layer 52 and there is no stopper film,
Over-etching can cause the thinly formed intrinsic base region 52i to disappear, and even if it does not disappear, when the intrinsic base region 52i is etched to a thinner thickness, the emitter region 58i is removed. There is a possibility that an emitter-collector short circuit may occur during solid-state diffusion, and there is a problem that a fine epi-base bipolar transistor formed by using a self-alignment process cannot be stably supplied.

Therefore, the present invention is capable of stably forming an epi-base bipolar transistor having uniform characteristics without etching the epi-base layer in the anisotropic etching for forming the base window. An object is to provide a method for forming an epi-base bipolar transistor by a matching process.

[0009]

1 (a) to 1 (l) are process sectional views for explaining the principle of the present invention. The above-mentioned problem is a method for manufacturing an epitaxial base bipolar transistor, which comprises forming a base layer (2) by epitaxial growth on a collector layer (1) made of silicon,
(2) a step of sequentially depositing a first silicon nitride film (3), a first silicon oxide film (4) and a first polysilicon film (5), [see (a) figure] Forming a base window (6) penetrating the polysilicon film (5) and the first silicon oxide film (4) and defining an intrinsic base region (2i) of the base layer (2), [(b) (See the figure) Step of selectively forming a second polysilicon film (7) on the side surface of the base window (6), (see (c) figure) Inner surface of the base window (6) and the first polysilicon film film
(5) a step of forming a second silicon nitride film (8) on it,
[See (d) figure] Step of selectively removing the second silicon nitride film (8) and the first polysilicon film (5) outside the transistor region (9), [see (e) figure] 1 silicon oxide film
Step of removing (4), [(f) FIG.] Step of completely oxidizing the first and second polysilicon films (5) and (7) to form a second silicon oxide film (10) , [See (g) figure] Step of removing the second silicon nitride film (8) and the first silicon nitride film (2) except on the intrinsic base region (2i), [see (h) figure] A third polysilicon film (11) having a thickness reaching the lower surface of the second silicon oxide film (10) and serving as a base extraction electrode is selectively formed on the exposed region of the base layer (2). Deposition step, [see (i) figure] Step of forming third silicon nitride film (12) on the entire surface of the substrate, [see (j) figure] Formation of emitter electrode inside transistor region (9) The third silicon nitride film (12) and the first silicon nitride film on the region (13)
(3) is removed to expose the surface of the intrinsic base region (2i), [see (k) figure] A fourth polysilicon film (14) serving as an emitter electrode is formed on the intrinsic base region (2i). Forming process,
A semiconductor device according to the present invention having a step [see (l) figure] of forming an emitter region (15) in an intrinsic base region (2i) by solid phase diffusion of impurities from the fourth polysilicon film (14). It is solved by the manufacturing method.

[0010]

That is, in the method of the present invention, the base window (6) (defining the intrinsic base region (2i)), which is the matching reference when forming the bipolar transistor by the self-alignment process, is anisotropically etched. Fig. 1 (b)
The first silicon nitride film is on the base layer (2) as shown in
It is covered with (3) and the intrinsic base region (2i) is not etched by overetching.
The thickness of (2i) is maintained to the end with the thickness accurately controlled by epitaxial growth. Therefore, according to the present invention, the epi-base bipolar transistor can be formed by the self-alignment process, and the epi-base bipolar transistor with a small parasitic element region can be formed, and at the same time, the thickness (corresponding to the depth) can be accurately adjusted. The emitter region (15) is formed in the controlled intrinsic base region (2i) to a highly precise depth by solid-phase diffusion from the polysilicon film (14) to be the emitter electrode, resulting in a very narrow and uniform base width. It is possible to stably obtain the epi-base transistor.

Therefore, according to the present invention, it is possible to stably manufacture a bipolar transistor having a uniform high speed operation speed.

[0012]

EXAMPLES The present invention will be described in detail below with reference to illustrated examples. 2, 3 and 4 are process sectional views of an embodiment of the method of the present invention. The same object is denoted by the same reference numeral throughout the drawings.

Referring to FIG. 2 (a), when a self-aligned type epi-base bipolar transistor is formed by the method of the present invention, as usual, for example, by ion implantation or the like on the p-type silicon substrate 21 surface having a specific resistance of about 15 to 20 Ωcm. , An n ⁺ type buried layer 22 having an impurity concentration of about 10 ¹⁸ to 10 ¹⁹ cm ^-3 is formed, and then an epitaxial growth is performed on this substrate to form an n type silicon layer having a specific resistance of about 0.3 Ωcm and a thickness of about 1.0 μm. The collector layer 23 is formed.

Next, as shown in FIG. 2B, after forming an element isolation region (not shown) for separating the collector layer 23 and the buried layer 22 for each transistor as usual, 1 × 10 1 is formed on the collector layer 23 by an epitaxial growth means. 1000 Å with an impurity concentration of about ¹⁸
After forming the p-type single crystal silicon base layer 24 to a thickness of about 1 μm, the first silicon nitride (Si ₃ N ₄ ) film 25 having a thickness of about 200 Å and the first silicon oxide having a thickness of about 3000 Å are formed by chemical vapor deposition.
A (SiO ₂ ) film 26 and a first poly-Si film 27 having a thickness of about 500Å are sequentially formed.

Referring to FIG. 2C, using a resist film (not shown) as a mask, anisotropic etching means such as reactive ion etching (RI) is used.
E) processing is performed to remove the first poly-Si film 27 and the first SiO ₂ film.
The film 26 is selectively removed to form a base window 28 having a width of, for example, 0.8 μm, which defines the intrinsic base region 24i. For this RIE treatment, for poly-Si, for example, [Cl ₂ + SiCl ₄ ]
Gas is used as an etching gas, and for SiO _2, for example, [CF ₄ + CHF ₃ ] gas is used as an etching gas.

During the RIE process for forming the base window 28, the epi base layer, that is, the p-type single crystal silicon base layer 24.
Since the upper part is covered with the first Si ₃ N ₄ film 25, the intrinsic base region 24i is not etched and the epitaxial growth thickness is maintained as it is.

Next, as shown in FIG. 2 (d), a second poly with a thickness of about 1000Å is formed on the entire surface of the substrate.
The Si film is vapor-phase grown, and then the entire surface is etched by RIE using the above etching gas to selectively form a second poly-Si film 29 having a thickness of about 1000Å on the side surface of the base window 28.

Then, referring to FIG. 2 (e), a thickness of 200 Å is formed on the entire surface of the substrate by vapor phase growth.
A second Si ₃ N ₄ film 30 is deposited to a degree.

Next, as shown in FIG. 3A, the second Si ₃ N ₄ film 30 and the first poly-Si film 30 below the second Si ₃ N ₄ film 30 are formed only on the transistor region 31 having a width of, for example, about 4 μm by RIE using a resist film (not shown) as a mask. Membrane 27
Patterning that leaves (including the second poly-Si film 29) is performed, and then wet etching is performed with a hydrofluoric acid-based solution to expose the exposed region and the first Si under the first poly-Si film 27.
The O ₂ film 26 is completely removed. Here, the second Si ₃ N ₄ film and the first poly-Si film 27 (including the second poly-Si film 29) therebelow.
An umbrella-shaped pattern is formed. The above Si ₃ N ₄
For etching the film 30, for example, [CF ₄ ] gas is used.

Next, as shown in FIG. 3B, the first and second poly-Si films 27 and 29 are all oxidized by thermal oxidation to form a _second SiO ₂ film 32. Where this second
The SiO ₂ film 32 and the second Si ₃ N ₄ film 30 are laminated to form an umbrella pattern.

Next, referring to FIG. 3 (c), a wet etching treatment with hot phosphoric acid is performed,
The second Si ₃ N ₄ film 30 is removed to remove the second SiO ₂ film 32.
An umbrella pattern is formed by the chisel. At this time, the exposed portion of the first Si ₃ N ₄ film 25 under the umbrella-shaped pattern is also removed at the same time. Avoid excessive over-etching
It is necessary to leave the first Si ₃ N ₄ film 25 on the intrinsic base region 24i in which the Si ₃ N ₄ film 25 and the second Si ₃ N ₄ film 30 are laminated.

Next, referring to FIG. 3 (d), on the exposed region of the base layer 24, for example, by a usual selective vapor deposition method using [SiH ₄ + B ₂ H ₆ + H ₂ ] gas,
For example, it has an impurity (boron) concentration of about 1 × 10 ²⁰ cm ^-3 ,
A base lead-out electrode having a thickness of about 3000 Å, whose upper surface reaches the lower surface of the umbrella-shaped pattern formed by the second SiO ₂ film 32, p ⁺
A third poly-Si film 33 of the mold is deposited.

Next, referring to FIG. 3 (e), a thickness of 200Å is formed on the entire surface of the substrate by vapor phase epitaxy.
A third Si ₃ N ₄ film 34 having a thickness of about 3 is formed.

Referring to FIG. 4A, the emitter electrode formation region 35 located inside the transistor region 31 is exposed on the third Si ₃ N ₄ film 34 by photolithography using a wet etching method using phosphoric acid. After forming the opening, and removing the third Si ₃ N ₄ film 34 on the side surface of the base window 28, R by the [CF ₄ ] gas is removed.
The first Si exposed on the bottom of the base window 28 by performing the IE process
_{The 3} N ₄ film 25 is selectively removed to expose the emitter formation region of the intrinsic base region 24i.

See FIG. 4 (b). Then, the intrinsic base region 24 exposed by a conventional selective vapor deposition method using, for example, [SiH ₄ + PH ₃ + H ₂ ] gas is used.
An n ⁺ -type fourth poly-Si film having an impurity (arsenic) concentration of about 1 × 10 ²⁰ cm ^-3 and a thickness of about 700 Å, that is, an n ⁺ -type poly-Si emitter electrode 34 is formed on i, and then a predetermined amount is formed. An intrinsic base region 24 having a thickness of about 1000Å is formed by heat treatment and solid phase diffusion from the n ⁺ type poly-Si emitter electrode 34.
An n ⁺ type emitter region 35 having a depth of, for example, about 500 to 700 Å is formed in i.

Incidentally, the collector extraction electrode is formed at a location in the front-back direction on the paper surface (not shown) separately from the above steps.
Then, although not shown, ordinary insulating film formation, wiring formation, etc. are performed to complete the self-aligned epi-base bipolar transistor.

The self-aligned epi-base bipolar transistor formed by the method of the present invention can also be formed by selective epitaxial growth of the emitter layer on the intrinsic base region exposed in the base window 28. In this case, Unlike the above embodiment, since the base width is defined with high accuracy only by the thickness of the epi base layer, the epi base layer can be formed thinner to easily form a bipolar transistor having higher speed and uniform operation characteristics. it can.

Furthermore, the base layer is made of a silicon-germanium mixed crystal (Si _{x having a} bandgap narrower than that of silicon).
Ge _x-1 x = 0 to ₁ ) formed on the collector layer made of silicon by a heteroepitaxial growth layer, and the emitter formed by a heteroepitaxial layer made of silicon on the intrinsic base region of the base layer through the base window. By forming it, the method of the present invention can be directly applied to the production of a hetero-bipolar transistor, which increases the injection efficiency of the emitter and further increases the speed.

[0029]

As is apparent from the above description, according to the method of the present invention, the epi-base bipolar transistor can be formed by the self-alignment process, and the epi-base bipolar transistor with a small parasitic element region can be formed. At the same time, the emitter region (15) is made to have a high precision depth by solid phase diffusion from the polysilicon film (14) which will be the emitter electrode to the intrinsic base region whose thickness (corresponding to the depth) is controlled with high precision. By forming it, it becomes possible to stably obtain an epi-base transistor having an extremely narrow and uniform base width.

Therefore, according to the present invention, it is possible to stably manufacture a high speed bipolar transistor having a uniform operation speed. Further, by forming the base layer by a heteroepitaxial growth layer of a semiconductor material having a bandgap narrower than that of silicon, it is possible to further increase the speed.

As described above, the present invention largely contributes to speeding up the circuit operation of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a process sectional view for explaining the principle of the present invention.

FIG. 2 is a process sectional view of an embodiment of the method of the present invention (No. 1)

FIG. 3 is a process sectional view of an embodiment of the method of the present invention (No. 2)

FIG. 4 is a process sectional view of an embodiment of the method of the present invention (No. 3)

FIG. 5 is a process sectional view of a conventional method.

[Description of Reference Signs] 1 collector layer 2 base layer (epi base layer) 2i intrinsic base region 3 first silicon nitride film 4 first silicon oxide film 5 first polysilicon film 6 base window 7 second polysilicon film 8 Second Silicon Nitride Film 9 Transistor Forming Area 10 Second Silicon Oxide Film 11 Third Polysilicon Film 12 Third Silicon Nitride Film 13 Emitter Electrode Forming Area 14 Fourth Polysilicon Film 15 Emitter Area

Claims (2)

[Claims] 1. A method of manufacturing an epitaxial base bipolar transistor, comprising a step of forming a base layer (2) on a collector layer (1) made of silicon by epitaxial growth, and first nitriding on the base layer (2). A step of sequentially depositing a silicon film (3), a first silicon oxide film (4) and a first polysilicon film (5), the first polysilicon film (5) and the first silicon oxide film
(4) penetrates through the base layer (2) and the intrinsic base region (2
forming a base window (6) defining i), a second polysilicon film selectively on the side surface of the base window (6)
(7) forming step, inner surface of the base window (6) and the first polysilicon film (5)
A step of forming a second silicon nitride film (8) thereon, a step of selectively removing the second silicon nitride film (8) and the first polysilicon film (5) outside the transistor region (9), A step of removing the first silicon oxide film (4), a step of completely oxidizing the first and second polysilicon films (5) and (7) to form a second silicon oxide film (10) , A step of removing the first silicon nitride film (3) other than on the second silicon nitride film (8) and the intrinsic base region (2i), selectively on the exposed region of the base layer (2) A step of depositing and forming a third polysilicon film (11) having a thickness reaching the lower surface of the second silicon oxide film (10) and serving as a base extraction electrode, a third polysilicon film (11) formed on the entire surface of the substrate. Forming a silicon nitride film (12), forming an emitter electrode inside the transistor region (9)
A step of removing the third silicon nitride film (12) and the first silicon nitride film (3) on (13) to expose the intrinsic base region (2i) surface, on the intrinsic base region (2i) A step of forming a fourth polysilicon film (14) serving as an emitter electrode on the semiconductor substrate, and solid phase diffusion of impurities from the fourth polysilicon film (14) to form an emitter region (15 ) Are formed, the manufacturing method of the semiconductor device characterized by the above-mentioned. 2. A semiconductor having a bandgap narrower than that of silicon is used for the base layer (2), and the emitter region is formed.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming (15) on the base layer (2) by selective heteroepitaxial growth of silicon.