JPH0429894U - - Google Patents
Info
- Publication number
- JPH0429894U JPH0429894U JP6996190U JP6996190U JPH0429894U JP H0429894 U JPH0429894 U JP H0429894U JP 6996190 U JP6996190 U JP 6996190U JP 6996190 U JP6996190 U JP 6996190U JP H0429894 U JPH0429894 U JP H0429894U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- detection
- frequency
- power
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 9
- 230000000630 rising effect Effects 0.000 claims description 4
- 238000007493 shaping process Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electric Clocks (AREA)
- Measurement Of Predetermined Time Intervals (AREA)
Description
第１図は本考案の構成を示すブロツク図、第２
図及び第３図は本考案をマイクロコンピユータに
よつて構成したときの動作を示すフローチヤート
である。
１……交流電源、２……内部発振器、３……波
形整形手段、４……立ち上がり検出手段、５……
分周手段、７……状態検出手段、８〜１０……第
１〜第３のパルスカウンタ（パルスカウンタ手段
）、１１……第２の切り換え手段（選択手段）、
１６……計時用計数手段。
Figure 1 is a block diagram showing the configuration of the present invention, Figure 2 is a block diagram showing the configuration of the present invention.
3 and 3 are flowcharts showing the operation of the present invention when it is implemented by a microcomputer. DESCRIPTION OF SYMBOLS 1...AC power supply, 2...Internal oscillator, 3...Waveform shaping means, 4...Rising detection means, 5...
Frequency dividing means, 7...state detection means, 8-10...first to third pulse counters (pulse counter means), 11...second switching means (selection means),
16...Counting means for timekeeping.
Claims (1)
流電源にて駆動されるデイジタルタイマであつて
、 前記交流電源が入力され、且つこの交流電源を
交流電源の周波数と同じ周波数を有する信号に整
形する波形整形手段と、 この整形された信号の立ち上がりを検出し、検
出信号を出力する立ち上がり検出手段と、 前記内部発振器からの出力パルスが入力され、
この入力信号に基づいて所定の周期毎に信号を出
力する分周手段と、 この分周手段からの出力信号に基づき前記立ち
上がり検出手段からの検出信号の計数を開始する
と共に、所定計数値の計数または前記分周手段か
らの次の出力信号に基づき計数内容がリセツトさ
れるパルスカウンタ手段と、 このパルスカウンタ手段のリセツト時における
計数値に基づき前記交流電源の状態を検出する状
態検出手段と、 この状態検出手段からの検出出力に基づき、前
記内部発振器出力パルス、または前記パルスカウ
ンタ手段のリセツトに応じた信号を選択する手段
と、 この選択手段からの信号に基づき基準時間を作
成する計時用計数手段と、 を備えるデイジタルタイマ。[Claims for Utility Model Registration] A digital timer that has an internal oscillator that outputs a predetermined pulse and is driven by an AC power source, the AC power being input and the frequency of the AC power being the same as the frequency of the AC power. waveform shaping means for shaping a signal to have the same frequency; rising detection means for detecting the rising edge of the shaped signal and outputting a detection signal; an output pulse from the internal oscillator is input;
a frequency dividing means that outputs a signal at each predetermined period based on the input signal; and a frequency dividing means that starts counting the detection signal from the rising edge detecting means based on the output signal from the frequency dividing means, and also starts counting the detection signal by a predetermined count value. or pulse counter means whose counting contents are reset based on the next output signal from the frequency dividing means; and state detection means which detects the state of the AC power supply based on the count value at the time of resetting the pulse counter means; means for selecting a signal corresponding to the internal oscillator output pulse or the reset of the pulse counter means based on the detection output from the state detection means; and a time counting means for creating a reference time based on the signal from the selection means. A digital timer equipped with and.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990069961U JP2509515Y2 (en) | 1990-06-29 | 1990-06-29 | Digital timer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990069961U JP2509515Y2 (en) | 1990-06-29 | 1990-06-29 | Digital timer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0429894U true JPH0429894U (en) | 1992-03-10 |
| JP2509515Y2 JP2509515Y2 (en) | 1996-09-04 |
Family
ID=31605718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990069961U Expired - Fee Related JP2509515Y2 (en) | 1990-06-29 | 1990-06-29 | Digital timer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2509515Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5753684A (en) * | 1980-09-17 | 1982-03-30 | Matsushita Electric Ind Co Ltd | Control circuit |
| JPH01127995A (en) * | 1987-11-13 | 1989-05-19 | Nec Corp | Clock circuit |
-
1990
- 1990-06-29 JP JP1990069961U patent/JP2509515Y2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5753684A (en) * | 1980-09-17 | 1982-03-30 | Matsushita Electric Ind Co Ltd | Control circuit |
| JPH01127995A (en) * | 1987-11-13 | 1989-05-19 | Nec Corp | Clock circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2509515Y2 (en) | 1996-09-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |