JPH04301904A - Pulse count type fm detection circuit - Google Patents

Abstract

PURPOSE:To improve various characteristics such as an output DC offset voltage, S/N and distortion rate at the pulse count type FM detection circuit. CONSTITUTION:An FM signal inputted from an input signal source 11 is compared with a first reference voltage at a first comparator circuit 12. A capacitor 14 is charged/discharged by the constant current output of the first comparator circuit 12, and the terminal voltage of the capacitor 14 is limited the amplitude by a limter circuit 16. The terminal voltage of the capacitor 14 limited the amplitude is impressed to a second comparator circuit 19 and compared with a third reference voltage V3. The input FM signal and the output signal of the second comparator circuit 19 are impressed to a pulse generating circuit, and an FM detection output signal is obtained at the output terminal.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a pulse count type FM
This invention relates to the improvement of a detection circuit, and particularly aims to provide a pulse count type FM detection circuit with excellent characteristics.

0002

2. Description of the Related Art Conventionally, a pulse count type FM detection circuit as shown in FIG. 2 has been known. In Figure 2, the signal source (
The input FM signal generated from 1) is connected to the input capacitor (2).
) to the positive input terminal of the first comparison circuit (3). The input FM signal is as shown in FIG. 3(A), and is compared with the first reference voltage V1 in the first comparison circuit (3). When the input FM signal is higher than the first reference voltage V1, the output of the first comparison circuit (3) becomes positive, and the capacitor (4) is charged with a time constant determined by the resistor (5) and the capacitor (4). Ru. Further, when the input FM signal is lower than the first reference voltage V1, the output of the first comparator circuit (3) becomes negative, and the capacitor (4) is discharged. Therefore,
The terminal voltage of the capacitor (4) is as shown in FIG. 3(b). Here, since the other end of the capacitor (4) is connected to a DC power supply that generates the second reference voltage V2, the terminal voltage of the capacitor (4) varies between positive and negative values around the second reference voltage V2. Change.

The terminal voltage of the capacitor (4) is applied to a second comparison circuit (6) and compared with a third reference voltage V3. Therefore, the output of the second comparison circuit (6) is as shown in Fig. 3 (c).
An output signal like this is generated. Furthermore, a second comparison circuit (6)
The output signal of is applied to one input terminal of the AND gate (7), and the input FM signal is applied to the other input terminal of the AND gate (7), so the output signal of the output terminal (8)
An output pulse as shown in FIG. 3(d) is obtained. By smoothing this output pulse, a low frequency output signal corresponding to the degree of modulation of the input FM signal can be obtained.

0004

[Problems to be Solved by the Invention] However, in the conventional pulse count type FM detection circuit shown in Fig. 2, in order to obtain a large output signal, the pulse width shown in Fig. 3 (d) must be widened; Therefore, the third reference voltage V3 shown in FIG.
value must be increased. However, Figure 3 (b)
As shown in , since the terminal voltage of the capacitor (4) changes smaller nearer to the tip of the waveform, the third reference voltage V
When the value of 3 is increased, the variation in the pulse width becomes large in accordance with the variation in the third reference voltage V3, and the variation in the output DC voltage also becomes large. Moreover, it becomes susceptible to the influence of noise contained in the input FM signal, leading to deterioration of the S/N ratio.

[0005]

[Means for Solving the Problems] The present invention has been made in view of the above-mentioned points, and includes a first comparison circuit that generates a constant current output, and a charging/discharging circuit that is charged and discharged by the constant current output of the first comparison circuit. It is characterized in that it includes a capacitor, a limiter circuit that limits the amplitude of the terminal voltage of the capacitor, and a pulse generation circuit that generates pulses in response to the output signal of the limiter circuit and the input FM signal.

[0006]

According to the present invention, first, the input FM signal is compared with the first reference voltage in the first comparator circuit, and a constant current output is generated from the first comparator circuit. The capacitor is
Since the battery is charged and discharged by the constant current output, its terminal voltage changes linearly. The limiter circuit limits the amplitude of the terminal voltage of the capacitor to a predetermined level. The pulse generation circuit generates pulses according to the input FM signal and the output signal of the limiter circuit.

[0007]

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention.
(11) is the intermediate frequency signal of FM radio broadcasting (10.7M
Hz±75KHz) and sub-signals of TV audio multiplex broadcasting (3
an input signal source (12) for generating an input FM signal such as 1.5KHz±10KHz), which compares the input FM signal with a first reference voltage V1 from a first power source (13) and generates a constant current; The first comparison circuit (14) is the first ratio rotation circuit (
12) A capacitor that is charged and discharged by the output constant current, (
15) is a second reference voltage V at the other end of the capacitor (14).
A second power supply (16) applying 2 to the capacitor (1
(19) is a limiter circuit consisting of first and second diodes (17) and (18) connected in parallel with 4) and in opposite directions to limit the amplitude of the terminal voltage of the capacitor (14); The terminal voltage of the capacitor (14) whose amplitude is limited by the limiter circuit (16) and the third power supply (
(20) is a second comparison circuit that compares the input FM signal with the third reference voltage V3 from the second comparison circuit (21);
This is an AND gate that performs AND with the output signal of 19).

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the waveform diagram shown in FIG. Now, if the input FM signal (non-modulated state) shown in FIG.
12), it is compared with the first reference voltage V1. The first reference voltage V1 is applied to the positive (+) and negative (-) input terminals of the first comparator circuit (12) via resistors (22) and (23) of equal value. Further, the first comparison circuit (1
2) has a push-pull type output stage, similar to commonly used comparison circuits, and when the voltage at the positive input terminal is greater than the voltage at the negative input terminal, the output constant current in the outflow direction is When the voltage at the positive input terminal is lower than the voltage at the negative input terminal, a constant output current is generated in the inflow direction. Therefore, input F
During the positive half cycle period of the M signal, the first comparison circuit (12
) generates a constant current in the outflow direction, and this constant current charges the capacitor (14) with a constant current. Also, during the negative half cycle period of the input FM signal, the first comparison circuit (
12) generates a constant current in the inflow direction, and this constant current causes constant current discharge of the capacitor (14). Furthermore, since the first and second diodes (17) and (18) are connected in parallel to the capacitor (14), the terminal voltage of the capacitor (14) is V2±VD (where VD is the diode voltage). The amplitude is limited by the forward voltage drop of Therefore, if the terminal voltage of the capacitor (14) is illustrated, it will be as shown in FIG. 4(b).

Capacitor (14) shown in FIG. 4(b)
The terminal voltage of is compared with the third reference voltage V3 in the second comparison circuit (19). The third reference voltage V3 is V2
Since it is set so that <V3<V2+VD, an output signal as shown in FIG. 4(c) is generated at the output terminal of the second comparison circuit (19). The output signal of the second comparison circuit (19) is applied to the AND gate (21) together with the input FM signal. Therefore, the output signal shown in Fig. 4 (d) is generated at the output terminal (24) connected to the output terminal of the AND gate (21), and if this output signal is smoothed, the FM detected low frequency I get a signal.

In the pulse count type detection circuit shown in FIG. 1, the terminal voltage of the capacitor (14) can be changed linearly as shown in FIG. , it becomes easier to set the third reference voltage V3, and variations are reduced. Therefore, S/
Since deterioration of N and distortion factor can be prevented, and variations in duty are reduced, generation of output DC offset voltage can be prevented.

FIG. 5 is a circuit diagram showing another embodiment of the present invention, which constitutes a double pulse count type FM detection circuit in contrast to the single type shown in FIG. In FIG. 5, the second comparison circuit (19) includes a first transistor (25) to which the input FM signal is applied to the base, and a second transistor (26) to which the first reference voltage V1 is applied to the base. one differential transistor pair (27), and a third transistor (27) to which the output signal of the limiter circuit (16) is applied to the base.
28) and a fourth transistor (29) to which the third reference voltage V3 is applied to the base;
Transistor (31) and limiter circuit (16) at the base
a sixth transistor (32) to which an output signal is applied; and a third differential transistor pair (33), the collector and base of which are
) and the collector of the seventh transistor (34) is connected to the collector of the fourth and sixth transistors (29) and (3
2) an eighth transistor (35) connected to the collector of
and an output transistor (37) whose base is connected to the collector of the eighth transistor (35).

The other parts in FIG. 5 are designated by the same reference numerals as in FIG. 1, and their explanation will be omitted. Input signal source (1
1), the input FM signal shown in Figure 6(a) is generated, and the first
If applied to the positive input terminal of the comparator circuit (12),
As in the case of FIG. 1, the output signal shown in FIG. 6(b) is generated at the output end of the limiter circuit (16). On the other hand, since the input FM signal is also applied to the base of the first transistor (25), the first transistor (25) is on and the second transistor (26) is off during the positive half cycle of the input FM signal. , the first transistor (25) during the negative half cycle.
is off, and the second transistor (26) is turned on.

[0013] Therefore, during the positive half cycle of the input FM signal, if its level is lower than the third reference voltage V3, the fourth transistor (29) is turned on and the base current of the output transistor (37) is aspirate. For that reason,
The output transistor (37) is turned on, and the output terminal (37) is turned on.
8), an H level output signal is generated. Also, input FM
During the positive half cycle of the signal, if its level is greater than the third reference voltage V3, the third transistor (28)
is turned on, and accordingly, the seventh and eighth transistors (34) and (35) constituting the current mirror circuit (36) are also turned on. Therefore, the output transistor (37) is turned off and the output terminal (38) becomes L level. Furthermore, during the negative half cycle of the input FM signal, if the level is higher than the fourth reference voltage V4, the sixth transistor (3
2) is turned on, and an H level output signal is generated at the output terminal (38). Furthermore, during the negative half cycle of the input FM signal, if its level is lower than the fourth reference voltage V4, the fifth transistor (31) is turned on, and the current mirror circuit (36) is configured accordingly. The seventh and eighth transistors (34) and (35) are also turned on, the output transistor (37) is turned off, and the output terminal (38) becomes L level. Therefore, a double pulse count type FM detection output signal is obtained at the output terminal (38) as shown in FIG. 6(c), and by smoothing this, an FM detected low frequency signal is obtained. The value of the fourth reference voltage V4 generated from the fourth power supply (39) in FIG. 5 is V3-V2=V2-V.
It is set to be 4.

The double pulse count type FM detection circuit shown in FIG. 5, like the circuit shown in FIG. 1, can linearly change the input signal to the second comparison circuit (19), so The reference voltages V3 and V4 can be easily set, and variations can be reduced. Furthermore, since it is a double pulse count type, FM detection efficiency is improved and FM detection accuracy is improved. Furthermore, since a double-balanced circuit is used as the second comparison circuit (19), it is resistant to variations and can minimize DC offset voltage.

[0015]

[Effects of the Invention] According to the present invention, since the capacitor is charged with a constant current using the first comparison circuit that generates a constant current according to the input FM signal, the terminal voltage of the capacitor is changed linearly. I can do it. Further, after limiting the amplitude of the terminal voltage of the capacitor using a limiter circuit, the second
Since the voltage is applied to the comparison circuit, the reference voltage can be easily set. Therefore, it is possible to improve the S/N ratio, improve the distortion factor, and reduce the output DC offset voltage.

[Brief explanation of drawings]

[Fig. 1] Circuit diagram showing one embodiment of the present invention

[Figure 2] Circuit diagram showing a conventional example

[Figure 3] Waveform diagram for explaining Figure 2

[Figure 4] Waveform diagram for explaining Figure 1

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

[Figure 6] Figure 5
Waveform diagram for explanation

[Explanation of symbols]

(11) Input signal source (12) First comparison circuit (14) Capacitor (16) Limiter circuit (19) (19) Second comparison circuit (21) And gate

Claims (3)

[Claims] 1. A pulse count type FM detection circuit for FM detecting an input FM signal, the circuit comprising: a first comparator circuit that generates a constant current output signal according to the input FM signal;
A capacitor that is charged and discharged by a constant current output signal of a comparison circuit, a limiter circuit that limits the amplitude of the terminal voltage of the capacitor, and a pulse generation circuit that generates a pulse in accordance with the output signal of the limiter circuit and the input FM signal. A pulse count type FM detection circuit characterized by comprising: 2. The pulse generation circuit includes a second comparator circuit that compares the limiter circuit with a reference voltage and generates an output, and an AND circuit that ANDs the output signal of the second comparator circuit and the input FM signal. 2. The pulse count type FM detection circuit according to claim 1, further comprising a gate. 3. The pulse generation circuit includes a first differential transistor pair to which an input FM signal is applied to one base and a first reference voltage applied to the other base, and an output signal of the limiter circuit to one base. a second differential transistor pair to which a second reference voltage is applied to the other base, a collector output signal of one of the first differential transistor pairs is applied to a common emitter, and an output of the limiter circuit to one base. a third differential pair of transistors, to which a signal is applied a third reference voltage to the base of the other and a collector output signal of the other of the first differential transistor pair to a common emitter;
means for commonly connecting one collector of the second differential transistor pair and the other collector of the third differential transistor pair; and means for commonly connecting the other collector of the second differential transistor pair and the third differential transistor pair. 2. The pulse count type FM detection circuit according to claim 1, further comprising means for commonly connecting one collector of the two collectors.