JPH0430207B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a field effect transistor (hereinafter referred to as MOST).
The present invention relates to an integrated circuit using an integrated circuit (hereinafter referred to as ``integrated circuit''), and in particular to a driver circuit with low power consumption.

A conventional circuit of this type is shown in Figure 1 (this is disclosed in USP 3506851, for example).
It was hot.

In the figure, 1 is the input terminal of the driver circuit,
2 is the output terminal, 3 is ON depending on the input state,
4 is the load MOST, 5 is the output load capacitance, and 6 is the level change of the output terminal 2.
A positive feedback capacitor feeds back to the gate of MOST4, 7 is a charging MOST that supplies voltage to the gate of MOST4, and 9 is a power supply terminal.

Next, the operation will be explained, but for the sake of convenience, all the circuit explanations will be based on the N-channel MOST. However, the circuit meaning is essentially the same even in the case of a P-channel MOST, and the present invention can be implemented in general circuits using IGFETs (insulated gate field effect transistors).

In Figure 1, when the input level is high
MOST3 turns ON, and the voltage at output terminal 2 becomes a low level close to the ground level. This level is
It is determined by the ratio of ON resistance of MOST3 and MOST4 (usually about 1:10).

Next, when the input level changes to a low level,
MOST3 turns OFF, and the level of output terminal 2 changes from low level to high level. This change is performed by charging the load capacitor 5 with the MOST 4. Therefore, the load capacity 5 can be increased at high speed.
In order to charge the MOST4, it is necessary to increase the charging current of the MOST4. However, in this case, when the input level is high, the current flowing through the MOSTs 4 and 3 will increase, and the power consumption of the driver circuit will increase.

In addition, in Figure 1, the feedback capacitor 6 changes the amount of change when the output level changes from a low level to a high level.
Feedback to the gate of MOST4 increases the voltage of node 8, which is the gate electrode of MOST4,
At the same time as increasing the charging current from MOST4
This is a capacitor to prevent the output voltage from decreasing due to the threshold voltage _VTH of MOST4. This capacitor 6 charges the output terminal 2 at high speed, and its level rises to the power supply voltage level. The above circuit operation is shown in the waveform diagram of FIG.

The circuit shown in FIG. 3 reduces the problem of power consumption, which is a drawback of the circuit shown in FIG. 1. This is a circuit in which buffer transistors 10 and 11 are connected between the output of the circuit shown in FIG. This circuit operates as follows.

As shown in the waveform diagrams in Figures 3 and 4, when the input level is high, node 1 is the same as in Figure 1.
3 is a low level close to the ground level. Accordingly
Since MOST11 is OFF and MOST10 is ON, the voltage at output terminal 2 becomes completely ground level (low level). Next, when the input level becomes low level, the node 13, which is the intermediate output terminal, changes from low level to high level as in FIG. However, in the circuit of FIG. 3, the load capacity to be charged by MOST4 is 12. Capacity 12
is mostly the gate capacitance of MOST11, and its value is usually much smaller than capacitance 5. Therefore, if the charging currents from the MOSTs in FIG. 1 and FIG. 3 are the same, node 13 in FIG. 3 will be charged faster than node 2 in FIG. 1. As a result, the MOST 11 driven by the voltage of the node 13 also charges the capacitor 5 at high speed. In other words, if the charging speed of the load capacitance 5 is made the same in the circuits of FIG. 1 and FIG.
This means that the circuit shown in the figure can consume less power.

However, in the circuit shown in Figure 3, the voltage at the output terminal 2 is lowered by the threshold voltage due to the threshold voltage of MOST 11, so the operating margin of the circuit driven by this signal with respect to the power supply voltage is reduced. There are drawbacks.

In view of the above points, the present invention provides a booster circuit to which an external power supply voltage is applied and generates a voltage higher than the external power supply voltage; one main electrode is connected to one of the voltage output terminals of the booster circuit; a first field effect transistor connected to an intermediate output terminal; and at least one field effect transistor connected between the intermediate output terminal and the other voltage output terminal of the booster circuit, having at least one input terminal and performing a logical operation. a third field effect transistor connected between the external power supply voltage terminal and the output terminal and having a gate connected to the intermediate output terminal; By making the voltage applied between the effect transistors higher than the sum of the threshold voltage of the third field effect transistor and the external power supply voltage, it is possible to reduce power consumption and output the output voltage up to the power supply voltage. The purpose is to provide a driver circuit that can.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 5, numerals 1 to 13 represent the same parts as those with the same reference numerals in FIG. however
The drain of MOST4 and the drain and gate of MOST7 are connected to node 19. The important components of this circuit are the booster circuit 20 and the first,
2nd, 3rd MOST 4, 3, 11, and 1st
The MOST 4 has one main electrode connected to one of the voltage output terminals 19 of the booster circuit 20, and the other main electrode connected to the intermediate output terminal 13. Also the second
The MOST 3 is connected between the intermediate output terminal 13 and the ground, which is the other voltage output terminal of the booster circuit 20, and has an input terminal 1 and performs a logical operation.The third MOST 11 is connected between the external power supply voltage V and the output terminal. 2 and intermediate output terminal 13 of the gate.
It is connected to the.

Further, 14 is a terminal to which an alternating current signal whose low level and high level are periodically repeated is applied, and a clock pulse φ is applied to this signal. 15 is a capacitor for boosting the voltage of node 19; 16 is a charging MOST for supplying charge to node 19; 1
7 is a rectifier to prevent the charge charged in node 19 by clock φ from returning to node 18.
MOST, 20 is clock φ and capacity 15,
As shown in FIG. 6, the booster circuit is composed of MOSTs 16 and 17 and generates a substantially constant voltage except for the initial stage of operation, 19 is the output node of the booster circuit 20, and 21 is the load of the booster circuit 20, which will be explained later. This is a capacitor for stabilizing voltage fluctuations at node 19 due to current.

First, the operation of the booster circuit 20 will be explained. As shown in the waveform diagram of FIG. 6, when a clock φ is periodically applied to the terminal 14 by an oscillation circuit provided on the integrated circuit or from the outside, the node 18 is charged through the capacitor 15 at the rising edge of the clock. The level of node 18 increases. At this time, node 18 acts as the drain and gate of MOST 17, MOST 17 is turned on, node 19 is also charged, and the level increases. Next, at the falling edge of the clock φ, charges are discharged from the node 18 through the capacitor 15 and the level of the node 18 decreases.
8 is the gate and source of MOST17, so
MOST17 is turned OFF. i.e. node 19
voltage does not change. No matter how many times the clock is applied, the above process is repeated and the level of node 19 gradually rises. If node 1
9 is not connected to the driver circuit shown in FIG. 5, its level is approximately V ₁₉ = 2 (V-
V _TH ). However, as shown in Fig. 5, the booster circuit 20
When a driver circuit as shown in the figure is connected as a load, when the input of the driver circuit is at a high level, current I flows through MOSTs 3 and 4, so the voltage at node 19 decreases. This situation is shown in FIG. FIG. 7 shows the relationship between the current flowing through the driver circuit (load current) and the output voltage of the booster circuit 20. In the figure, the characteristic changes when I= _IB because when the load current increases and the output voltage drops to V-2V _TH , the current supplied from the MOST 16 is added.

The operation of the driver circuit portion in FIG. 5 is the same as that of the circuit in FIG. Now, the current flowing through MOST3 and 4 in Figure 5 is expressed as I _A in Figure 7.
Assuming that the input becomes low level, the drain voltage of MOST4 becomes more than V + V _TH as shown in Figure 7, so a voltage of more than V + V TH appears at node 13, which is the _intermediate output terminal. It turns out. As a result, the drop in MOST 11 due to V _TH is compensated, and the output node 2 is brought up to the power supply voltage level, thus improving the drawbacks of the conventional circuit. In the above embodiment, there is a second terminal that performs a logical operation between the intermediate output terminal 13 and the ground, which is the other voltage output terminal of the booster circuit 20.
Although only one MOST3 was connected, this second
A plurality of MOSTs may be connected in series or parallel, or in series, parallel, or combinations.

FIG. 8 is a circuit diagram showing another embodiment of the present invention.

The difference between the circuit in Figure 8 and the circuit in Figure 5 is MOST
11 is connected to the output of the booster circuit 20 instead of the power supply. In this circuit, for example, when the voltage at node 19 is set to V+2V _TH , the output voltage at node 2 reaches V+V _TH , so that the margin for the power supply voltage can be greater than in the circuit of FIG.

FIG. 9 is a circuit diagram showing another embodiment of the present invention. The difference between the circuit in Figure 9 and the circuit in Figure 8 is
Capacitor 6 for boosting the gate voltage of MOST4
is connected between the output of an inverter consisting of MOSTs 22 and 23 whose input is terminal 1 and the gate electrode (node 8) of MOST 4. The purpose of this circuit is to prevent the output node 25 of the inverter consisting of the MOSTs 22 and 23 from being loaded with anything other than the feedback capacitance 6 and the parasitic capacitance 24, thereby increasing the rising speed of the node 25 and boosting the voltage at the node 8 by the capacitance 6. The goal is to make it faster.
As a result, the rising speed of the node 13 becomes faster, and the rising speed of the output node 2 also becomes faster.

FIG. 10 is a circuit diagram showing another embodiment of the present invention. The difference between FIG. 10 and FIG. 9 is that a logic circuit is configured in the input section, and the output node has the AND of the inputs to input terminals 1a and 1b and the input terminal 1.
The NOR value of the input to c comes out. It can be easily inferred from the above explanation that the present invention can be applied to a logic circuit in which a plurality of inputs are combined as shown in FIG.

FIG. 11 is a circuit diagram showing another embodiment of the present invention. The difference between Figure 11 and Figure 9 is that the gate and drain of MOST7 that charges node 8 are connected to power supply terminal 9.
is connected to.

In this case, substantially the same result as in FIG. 9 can be obtained in terms of circuit operation, only that the initial voltage before node 8 is boosted is V-V _TH .

As described above, according to the present invention, the power supply voltage and
By using a voltage boosted above the sum of the MOST threshold voltages as the driver power supply voltage, the driver output voltage can be made higher than the power supply voltage, resulting in lower power consumption and operating margin for the power supply voltage. It has the effect of increasing the degree of

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional driver circuit.
2 is a waveform diagram for explaining the circuit operation of FIG. 1, FIG. 3 is a circuit diagram showing a conventional driver circuit, FIG. 4 is a waveform diagram for explaining the circuit operation of FIG. 5 is a circuit diagram showing an embodiment of the present invention, FIG. 6 is a waveform diagram for explaining the circuit operation of FIG. 5, and FIG. 7 is a characteristic diagram for explaining the circuit operation of FIG. 5. 8 to 11 are all circuit diagrams showing embodiments of the present invention. V...External power supply voltage, 4...First MOST, 3...
Second MOST, 11... Third MOST, 20... Boost circuit, 15... Capacitor, 17... Switching element,
φ…AC signal.

Claims (1)

[Scope of Claims] 1. A step-up circuit that includes a capacitor and a switching element and generates a substantially constant voltage higher than a first external power supply voltage in response to an AC signal, and one main electrode. is connected to the voltage output terminal of the step-up circuit, and the other main electrode is connected to the intermediate output terminal, and the intermediate output terminal is connected between the intermediate output terminal and a terminal to which a second external power supply voltage is applied. at least one second field effect transistor having at least one input terminal and performing a logical operation; and a third field effect transistor connected between the external power supply voltage terminal and the output terminal and having a gate connected to the intermediate output terminal. a field effect transistor, and the voltage applied between the first and second field effect transistors is higher than the sum of the threshold voltage of the third field effect transistor and the external power supply voltage. Characteristic driver circuit. 2. A step-up circuit that includes a capacitor and a switching element and generates a substantially constant voltage higher than the first external power supply voltage by receiving an AC signal; one main electrode is connected to the voltage of the step-up circuit; a first field effect transistor whose other main electrode is connected to the intermediate output terminal; and at least one input terminal connected between the intermediate output terminal and a terminal to which a second external power supply voltage is applied. at least one second field effect transistor having a terminal and performing a logical operation; and a third field effect transistor connected between the voltage output terminal and the output terminal of the booster circuit and having a gate connected to the intermediate output terminal. A driver, characterized in that the voltage applied between the first and second field effect transistors is higher than the sum of the threshold voltage of the third field effect transistor and the external power supply voltage. circuit.